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1. 发明授权

US5124014A Method of forming oxide layers by bias ECR plasma deposition 失效
标题翻译：通过偏压ECR等离子体沉积法形成氧化物层的方法
公开(公告)号：US5124014A
公开(公告)日：1992-06-23
申请号：US684453
申请日：1991-04-11
申请人： Pang-Dow Foo , Ajit S. Manocha , John F. Miner , Chien-Shing Pai
发明人： Pang-Dow Foo , Ajit S. Manocha , John F. Miner , Chien-Shing Pai
IPC分类号： C23C16/40 , C23C16/511 , H01L21/316
CPC分类号： H01L21/02164 , C23C16/402 , C23C16/511 , H01L21/02216 , H01L21/02274 , H01L21/31612
摘要： A method of forming silicon dioxide layers by bias ECR is described. The layers are formed by reacting oxygen with TEOS or TMCTS. High-quality, void-free layerc can be formed over conductor patterns having high-aspect-ratio intermetallic spacings.
摘要翻译：描述了通过偏压ECR形成二氧化硅层的方法。这些层通过氧气与TEOS或TMCTS反应而形成。可以在具有高纵横比金属间距的导体图案上形成高质量，无空隙的层。

2. 发明授权

US5057455A Formation of integrated circuit electrodes 失效
标题翻译：集成电路电极的形成
公开(公告)号：US5057455A
公开(公告)日：1991-10-15
申请号：US443766
申请日：1989-11-30
申请人： Pang-Dow Foo , William T. Lynch , Chien-Shing Pai
发明人： Pang-Dow Foo , William T. Lynch , Chien-Shing Pai
IPC分类号： H01L29/73 , H01L21/285 , H01L21/311 , H01L21/3213 , H01L21/331 , H01L21/762 , H01L21/768 , H01L21/8249 , H01L27/06 , H01L29/732
CPC分类号： H01L21/76802 , H01L21/28525 , H01L21/31144 , H01L21/32139 , H01L21/762 , H01L21/8249 , Y10S438/97
摘要： In the fabrication of electrodes for transistors in the BiCMOS integrated circuit, vertical windows etched in a relatively thick TEOS (or other suitable dielectric) layer, located on a relatively thin polysilicon layer, in turn located on relatively tin oxide layer areas and on relatively thick oxide layer areas, are used to define areas where polysilicon electrode material is to remain. Polysilicon is deposited in the windows in the relatively thick insulating layer, to form the basis for the desired electrode in each window. The relatively thin polysilicon layer (or, alternatively an .alpha.-amorphous silicon layer) is thereafter used as an etch stop during the subsequent removal of the relatively thick dielectric layer. Thereafter both MOS and bipolar transistors can be fabricated using the windows to define the extents of the gate regions of the MOS transistors and the extents of the emitter regions of the bipolar transistors. In addition, both the source and drain electrodes of the MOS transistors and the base electrodes of the bipolar transistors can then be simultaneously formed in a self-aligned manner without the need for etching into the underlying semiconductor substrate in which the integrated circuit is being formed.
摘要翻译：在BiCMOS集成电路中用于晶体管的电极的制造中，在位于相对较薄的多晶硅层上的相对较厚的TEOS（或其它合适的电介质）层中蚀刻的垂直窗口依次位于相对锡氧化物层区域上并且相对较厚氧化物层区域用于限定保留多晶硅电极材料的区域。多晶硅沉积在相对厚的绝缘层中的窗口中，以形成每个窗口中所需电极的基础。此后，在相对较厚的电介质层的去除期间，相对薄的多晶硅层（或者可选地，α-非晶硅层）被用作蚀刻停止层。此后，可以使用窗口来制造MOS和双极晶体管，以限定MOS晶体管的栅极区域的范围和双极晶体管的发射极区域的范围。此外，MOS晶体管的源电极和漏电极以及双极晶体管的基极可以以自对准的方式同时形成，而不需要蚀刻到其中形成集成电路的下面的半导体衬底。

3. 发明授权

US5616518A Process for fabricating integrating circuits 失效
标题翻译：集成电路的制造工艺
公开(公告)号：US5616518A
公开(公告)日：1997-04-01
申请号：US333900
申请日：1994-11-03
申请人： Pang-Dow Foo , Chien-Shing Pai
发明人： Pang-Dow Foo , Chien-Shing Pai
IPC分类号： H01L21/285 , C23C16/32 , C23C16/50 , C23C16/511 , H01L21/28 , H01L21/768 , H01L21/441
CPC分类号： H01L21/76843
摘要： Integrated circuits employing titanium nitride are significantly improved by using a specific method for formation of the titanium nitride in the device fabrication. In particular, a plasma such as one formed in an electron cyclotron resonance apparatus is employed to dissociate a source of nitrogen and a source of hydrogen and the dissociation products are combined at the integrated circuit deposition substrate with titanium tetrachloride. The resulting deposition is essentially devoid of chlorine and has advantageous step-coverage properties.
摘要翻译：使用氮化钛的集成电路通过在器件制造中使用用于形成氮化钛的具体方法而显着改善。特别地，使用诸如在电子回旋共振装置中形成的等离子体来解离氮源和氢源，并且解离产物在集成电路沉积衬底与四氯化钛组合。所得到的沉积物基本上不含氯，并且具有有利的步骤覆盖性能。

4. 发明授权

US5643838A Low temperature deposition of silicon oxides for device fabrication 失效
标题翻译：用于器件制造的氧化硅的低温沉积
公开(公告)号：US5643838A
公开(公告)日：1997-07-01
申请号：US116309
申请日：1993-09-03
申请人： Robert Earl Dean , Pang-Dow Foo , Earl Ryan Lory , Leonard Jay Olmer
发明人： Robert Earl Dean , Pang-Dow Foo , Earl Ryan Lory , Leonard Jay Olmer
IPC分类号： H01L21/316 , H01L21/02
CPC分类号： H01L21/02164 , H01L21/02129 , H01L21/02216 , H01L21/02274 , H01L21/31608
摘要： The use of a deposition process involving a plasma struck in a gas including tetraethoxysilane and a source of oxygen yields, at low temperatures, conformal coatings of silicon dioxide. This process has significant implications for semiconductor device fabrication involving the deposition of a dielectric over a metallic non-planar structure.
摘要翻译：使用涉及包含四乙氧基硅烷和氧源的气体中的等离子体的沉积方法在低温下产生二氧化硅的共形涂层。该过程对于涉及在金属非平面结构上沉积电介质的半导体器件制造具有重要意义。

5. 发明授权

US4871420A Selective etching process 失效
标题翻译：选择性蚀刻工艺
公开(公告)号：US4871420A
公开(公告)日：1989-10-03
申请号：US150490
申请日：1988-02-10
申请人： Frank B. Alexander, Jr. , Pang-Dow Foo , Ronald J. Schutz
发明人： Frank B. Alexander, Jr. , Pang-Dow Foo , Ronald J. Schutz
IPC分类号： H01L21/3065 , H01L21/3213
CPC分类号： H01L21/32137 , H01L21/3065
摘要： By adjusting the AC field conditions, i.e., by grounding the environment of a substrate being etched with a chlorine-containing plasma, a significant increase in etch selectivity is achieved. By applying a similar AC field adjustment to the reaction chamber surfaces, excellent etch uniformity is achieved in conjunction with excellent selectivity.
摘要翻译：通过调整AC场条件，即通过用含氯等离子体接地被蚀刻的衬底的环境来实现蚀刻选择性的显着增加。通过对反应室表面施加类似的AC场调整，结合优异的选择性实现了优异的蚀刻均匀性。

6. 发明授权

US06667516B2 RF LDMOS on partial SOI substrate 失效
公开(公告)号：US06667516B2
公开(公告)日：2003-12-23
申请号：US10186528
申请日：2002-07-01
申请人： Shuming Xu , Hanhua Feng , Pang-Dow Foo
发明人： Shuming Xu , Hanhua Feng , Pang-Dow Foo
IPC分类号： H01L2994
CPC分类号： H01L29/66659 , H01L29/0653 , H01L29/4175 , H01L29/41766 , H01L29/66636 , H01L29/7835 , Y10S438/923
摘要： In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, this structure has poor high frequency characteristics. Also in the prior art, good high frequency performance has been achieved by introducing a dielectric layer immediately below the source/drain regions (SOI) but this structure has poor power handling capabilities. The present invention achieves both good high frequency behavior as well as good power capability in the same device. Instead of inserting a dielectric layer over the entire cross-section of the device, the dielectric layer is limited to being below the heavily doped section of the drain with a small amount of overlap into the lightly doped section. The structure is described in detail together with a process for manufacturing it.

7. 发明授权

US06461902B1 RF LDMOS on partial SOI substrate 失效
标题翻译： RF LDMOS在部分SOI衬底上
公开(公告)号：US06461902B1
公开(公告)日：2002-10-08
申请号：US09618263
申请日：2000-07-18
申请人： Shuming Xu , Hanhua Feng , Pang-Dow Foo
发明人： Shuming Xu , Hanhua Feng , Pang-Dow Foo
IPC分类号： H01L2100
CPC分类号： H01L29/66659 , H01L29/0653 , H01L29/4175 , H01L29/41766 , H01L29/66636 , H01L29/7835 , Y10S438/923
摘要： In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, this structure has poor high frequency characteristics. Also in the prior art, good high frequency performance has been achieved by introducing a dielectric layer immediately below the source/drain regions (SOI) but this structure has poor handling capabilities. The present invention achieves both good high frequency behavior as well as good power capability in the same device. Instead of inserting a dielectric layer over the entire cross-section of the device, the dielectric layer is limited to being below the heavily doped section of the drain with a small amount of overlap into the lightly doped section. The structure is described in detail together with a process for manufacturing it.
摘要翻译：在现有技术中，能够处理高功率的LDMOSFET器件已经通过将源极接触定位在器件的底表面上，通过连接到源极区域通过沉降片而实现良好的散热。然而，该结构具有差的高频特性。同样在现有技术中，通过在源极/漏极区域（SOI）之下引入介电层已经实现了良好的高频性能，但是该结构具有差的处理能力。本发明在同一设备中实现了良好的高频行为以及良好的功率能力。代替在器件的整个横截面上插入电介质层，电介质层被限制在漏极的重掺杂部分之下，在轻掺杂部分中具有少量的重叠。详细描述该结构及其制造方法。

8. 发明授权

US5120680A Method for depositing dielectric layers 失效
标题翻译：介电层沉积方法
公开(公告)号：US5120680A
公开(公告)日：1992-06-09
申请号：US555128
申请日：1990-07-19
申请人： Pang-Dow Foo , Tai-Chan D. Huo , Man F. Yan
发明人： Pang-Dow Foo , Tai-Chan D. Huo , Man F. Yan
IPC分类号： C23C16/40 , C23C16/509 , H01L21/31 , H01L21/316 , H01L21/768
CPC分类号： H01L21/02164 , C23C16/402 , C23C16/5096 , H01L21/02216 , H01L21/02274 , H01L21/31612 , H01L21/76837 , Y10S148/118
摘要： Disclosed is a method for forming a silicon dioxide layer on a substrate by radio-frequency deposition from a plasma comprising oxygen, argon, and tetraethyl orthosilicate (TEOS) or tetramethyl cyclotetrasiloxane (TMCTS). A negative bias is imparted to the substrate. The resulting ion bombardment induces surface migration. Because TEOS and TMCTS have a relatively high mean free path for surface migration, the filling of soft spots and key holes is promoted.
摘要翻译：公开了一种通过从包含氧，氩和原硅酸四乙酯（TEOS）或四甲基环四硅氧烷（TMCTS）的等离子体的射频沉积在基板上形成二氧化硅层的方法。向衬底赋予负偏压。所产生的离子轰击引起表面迁移。由于TEOS和TMCTS具有相对较高的表面迁移平均自由程，因此促进了软点和键孔的填充。

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