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1. 发明授权

US06391773B2 Method and materials for through-mask electroplating and selective base removal 失效
标题翻译：用于通孔电镀和选择性基底去除的方法和材料
公开(公告)号：US06391773B2
公开(公告)日：2002-05-21
申请号：US09733188
申请日：2000-12-09
申请人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , Roy Carruthers , Alfred Grill , Katherine Lynn Saenger
发明人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , Roy Carruthers , Alfred Grill , Katherine Lynn Saenger
IPC分类号： H01L2144
CPC分类号： H01L28/60 , H01L21/2885 , H01L28/75
摘要： Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers. Similarly, the alloying or intermixing may be accomplished before or after plating base removal for structures deposited by through-mask plating.
摘要翻译：选择多层金属材料，使得材料将在快速热退火条件下合金或混合。优选选择多层的单个材料，使得可以通过湿化学或电化学蚀刻相对于其它材料选择性地蚀刻至少一种材料。对于电镀应用，合金电镀基体材料将承受原始电沉积材料的一些耐蚀刻性，使得可以进行电镀基底的选择性湿法蚀刻而没有实质的底切。此外，分级组合物合金对于电极的形成和使用将表现出其它有利的物理和化学性质。合金化或混合可以在材料图案化之前或之后完成，例如其中作为覆盖层沉积的材料。类似地，合金化或混合可以在通过通过掩模电镀沉积的结构的电镀基底去除之前或之后完成。

2. 发明授权

US06188120B1 Method and materials for through-mask electroplating and selective base removal 失效
标题翻译：用于通孔电镀和选择性基底去除的方法和材料
公开(公告)号：US06188120B1
公开(公告)日：2001-02-13
申请号：US08805403
申请日：1997-02-24
申请人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , Roy Carruthers , Alfred Grill , Katherine Lynn Saenger
发明人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , Roy Carruthers , Alfred Grill , Katherine Lynn Saenger
IPC分类号： H01L27108
CPC分类号： H01L28/60 , H01L21/2885 , H01L28/75
摘要： Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers. Similarly, the alloying or intermixing may be accomplished before or after plating base removal for structures deposited by through-mask plating.
摘要翻译：选择多层金属材料，使得材料将在快速热退火条件下合金或混合。优选选择多层的单个材料，使得可以通过湿化学或电化学蚀刻相对于其它材料选择性地蚀刻至少一种材料。对于电镀应用，合金电镀基体材料将承受原始电沉积材料的一些耐蚀刻性，使得可以进行电镀基底的选择性湿法蚀刻而没有实质的底切。此外，分级组合物合金对于电极的形成和使用将表现出其它有利的物理和化学性质。合金化或混合可以在材料图案化之前或之后完成，例如其中作为覆盖层沉积的材料。类似地，合金化或混合可以在通过通过掩模电镀沉积的结构的电镀基底去除之前或之后完成。

3. 发明授权

US5789320A Plating of noble metal electrodes for DRAM and FRAM 失效
标题翻译：电镀DRAM和FRAM的贵金属电极
公开(公告)号：US5789320A
公开(公告)日：1998-08-04
申请号：US636456
申请日：1996-04-23
申请人： Panayotis Constantinou Andricacos , James Hartfiel Comfort , Alfred Grill , David Edward Kotecki , Vishnubhai Vitthalbhai Patel , Katherine Lynn Saenger , Alejandro Gabriel Schrott
发明人： Panayotis Constantinou Andricacos , James Hartfiel Comfort , Alfred Grill , David Edward Kotecki , Vishnubhai Vitthalbhai Patel , Katherine Lynn Saenger , Alejandro Gabriel Schrott
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/44
CPC分类号： H01L27/1085 , H01L28/60
摘要： Noble metal plating on a preexisting seed layer is used in the fabrication of electrodes for DRAM and FRAM. The plating may be spatially selective or nonselective. In the nonselective case, a blanket film is first plated and then patterned after deposition by spatially selective material removal. In the selective case, the plated deposits are either selectively grown in lithographically defined areas by a through-mask plating technique, or selectively grown as a conformal coating on the exposed regions of a preexisting electrode structure. A diamond-like carbon mask can be used in the plating process. A self-aligned process is disclosed for selectively coating insulators in a through-mask process.
摘要翻译：用于DRAM和FRAM的电极的制造中使用预先存在的种子层上的贵金属电镀。电镀可以是空间选择性的或非选择性的。在非选择性情况下，首先将覆盖膜镀覆，然后通过空间选择性材料去除在沉积后进行图案化。在选择性情况下，电镀沉积物可以通过通孔掩模技术在光刻定义的区域中选择性地生长，或者在预先存在的电极结构的暴露区域上选择性地生长为保形涂层。在电镀工艺中可以使用类金刚石碳膜。公开了一种自对准工艺，用于在通过掩模工艺中选择性地涂覆绝缘体。

4. 发明授权

US06773982B2 Feram cell with internal oxygen source and method of oxygen release 失效
标题翻译：具有内氧源的Feram电池和释氧方法
公开(公告)号：US06773982B2
公开(公告)日：2004-08-10
申请号：US09927694
申请日：2001-08-10
申请人： Charles Thomas Black , Cyril Cabral, Jr. , Alfred Grill , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
发明人： Charles Thomas Black , Cyril Cabral, Jr. , Alfred Grill , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： An integrated ferroelectric/CMOS structure which comprises at least a ferroelectric material, a pair of electrodes in contact with opposite surfaces of the ferroelectric material, where the electrodes do not decompose at deposition or annealing, and an oxygen source layer in contact with at least one of said electrodes, said oxygen source layer being a metal oxide which at least partially decomposes during deposition and/or subsequent processing is provided as well as a method of fabricating the same.
摘要翻译：一种集成铁电/ CMOS结构，其至少包括铁电材料，与所述铁电材料的相对表面接触的一对电极，其中所述电极在沉积或退火时不分解，以及氧源层与至少一个的所述电极，所述氧源层是在沉积期间和/或后续处理中至少部分分解的金属氧化物以及其制造方法。

5. 发明授权

US06388285B1 Feram cell with internal oxygen source and method of oxygen release 失效
标题翻译：具有内氧源的Feram电池和释氧方法
公开(公告)号：US06388285B1
公开(公告)日：2002-05-14
申请号：US09325857
申请日：1999-06-04
申请人： Charles Thomas Black , Cyril Cabral, Jr. , Alfred Grill , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
发明人： Charles Thomas Black , Cyril Cabral, Jr. , Alfred Grill , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
IPC分类号： H01L29788
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： An integrated ferroelectric/CMOS structure which comprises at least a ferroelectric material, a pair of electrodes in contact with opposite surfaces of the ferroelectric material, where the electrodes do not decompose at deposition or annealing, and an oxygen source layer in contact with at least one of said electrodes, said oxygen source layer being a metal oxide which at least partially decomposes during deposition and/or subsequent processing is provided as well as a method of fabricating the same.
摘要翻译：一种集成铁电/ CMOS结构，其至少包括铁电材料，与所述铁电材料的相对表面接触的一对电极，其中所述电极在沉积或退火时不分解，以及氧源层与至少一个的所述电极，所述氧源层是在沉积期间和/或后续处理中至少部分分解的金属氧化物以及其制造方法。

6. 发明授权

US5825609A Compound electrode stack capacitor 失效
标题翻译：复合电极堆叠电容器
公开(公告)号：US5825609A
公开(公告)日：1998-10-20
申请号：US636457
申请日：1996-04-23
申请人： Panayotis Constantinou Andricacos , David Edward Kotecki , Katherine Lynn Saenger
发明人： Panayotis Constantinou Andricacos , David Edward Kotecki , Katherine Lynn Saenger
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792 , H01G4/06
CPC分类号： H01L28/82 , H01L21/76849 , H01L21/7687 , H01L27/1085 , H01L28/91 , H01L28/55
摘要： This invention is directed to a semiconductor memory device including a storage element having a ferroelectric material or a capacitor dielectric material between a top (plate) electrode and a bottom (stack) electrode. In particular, the invention pertains to the design and fabrication of the stack electrode, which is described as compound because it is comprised of two or more materials which are either patterned separately (with at least one material being deposited and patterned prior to the deposition of the others), or arranged so that each of the component materials significantly contributes to the area over which the ferroelectric or capacitor dielectric is initially deposited. These compound stack electrodes may offer ease in processing, more economical use of noble metal materials, and potentially increased mechanical stability (e.g., resistance to hillocking) relative to solid, single-material electrodes of the same dimensions.
摘要翻译：本发明涉及一种半导体存储器件，其包括在顶部（板）电极和底部（堆叠）电极之间具有铁电材料或电容器电介质材料的存储元件。特别地，本发明涉及堆叠电极的设计和制造，其被描述为化合物，因为它由两种或更多种材料组成，这两种或多种材料是单独图案化的（至少一种材料在沉积之前沉积和图案化其他），或者被布置成使得每个组分材料显着地有助于初始沉积铁电体或电容器电介质的区域。相对于相同尺寸的固体单材料电极，这些复合堆叠电极可以提供易于处理，更经济地使用贵金属材料以及潜在的增加的机械稳定性（例如抵抗小丘）。

7. 发明授权

US5998250A Compound electrode stack capacitor 失效
标题翻译：复合电极堆叠电容器
公开(公告)号：US5998250A
公开(公告)日：1999-12-07
申请号：US62031
申请日：1998-04-17
申请人： Panayotis Constantinou Andricacos , David Edward Kotecki , Katherine Lynn Saenger
发明人： Panayotis Constantinou Andricacos , David Edward Kotecki , Katherine Lynn Saenger
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： H01L28/82 , H01L21/76849 , H01L21/7687 , H01L27/1085 , H01L28/91 , H01L28/55
摘要： This invention is directed to a semiconductor memory device including a storage element comprising a ferroelectric material or a capacitor dielectric material between a top (plate) electrode and a bottom (stack) electrode. In particular, the invention pertains to the design and fabrication of the stack electrode, which is described as compound because it is comprised of two or more materials which are either patterned separately (with at least one material being deposited and patterned prior to the deposition of the others), or arranged so that each of the component materials significantly contributes to the area over which the ferroelectric or capacitor dielectric is initially deposited. These compound stack electrodes may offer ease in processing, more economical use of noble metal materials, and potentially increased mechanical stability (e.g., resistance to hillocking) relative to solid, single-material electrodes of the same dimensions.
摘要翻译：本发明涉及一种半导体存储器件，其包括在顶部（板）电极和底部（堆叠）电极之间包括铁电材料或电容器电介质材料的存储元件。特别地，本发明涉及堆叠电极的设计和制造，其被描述为化合物，因为它由两种或更多种材料组成，这两种或多种材料是单独图案化的（至少一种材料在沉积之前沉积和图案化其他），或者被布置成使得每个组分材料显着地有助于初始沉积铁电体或电容器电介质的区域。相对于相同尺寸的固体单材料电极，这些复合堆叠电极可以提供易于处理，更经济地使用贵金属材料以及潜在的增加的机械稳定性（例如抵抗小丘）。

8. 发明授权

US07217969B2 Flip FERAM cell and method to form same 失效
标题翻译：翻转FERAM细胞和方法形成相同
公开(公告)号：US07217969B2
公开(公告)日：2007-05-15
申请号：US10384002
申请日：2003-03-07
申请人： James William Adkisson , Charles Thomas Black , Alfred Grill , Randy William Mann , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
发明人： James William Adkisson , Charles Thomas Black , Alfred Grill , Randy William Mann , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
IPC分类号： H01L29/76
CPC分类号： H01L28/55 , H01L27/0629 , H01L27/11502 , H01L27/11507 , Y10S438/977
摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.
摘要翻译：提供了一种形成集成的铁电/ CMOS结构的方法，其有效地分离不兼容的高温沉积和退火工艺。本发明的方法包括分别形成CMOS结构和铁电输送晶片。然后使这些分离的结构与每个结构接触，并且通过使用低温退火步骤将输送晶片的铁电体膜结合到CMOS结构的上导电电极层。然后去除输送晶片的一部分，提供集成的FE / CMOS结构，其中铁电电容器形成在CMOS结构的顶部。电容器通过CMOS结构的所有布线级与CMOS结构的晶体管接触。

9. 发明授权

US06815329B2 Multilayer interconnect structure containing air gaps and method for making 有权
标题翻译：包含气隙的多层互连结构和制造方法
公开(公告)号：US06815329B2
公开(公告)日：2004-11-09
申请号：US10117797
申请日：2002-04-02
申请人： Katherina E. Babich , Roy Arthur Carruthers , Timothy Joseph Dalton , Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Ebony Lynn Mays , Laurent Perraud , Sampath Purushothaman , Katherine Lynn Saenger
发明人： Katherina E. Babich , Roy Arthur Carruthers , Timothy Joseph Dalton , Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Ebony Lynn Mays , Laurent Perraud , Sampath Purushothaman , Katherine Lynn Saenger
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/7681 , H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.
摘要翻译：描述了一种新颖的含气隙的互连布线结构，其在通孔级中结合有固体低k电介质，并且在布线层中结合了复合固体和气隙电介质。还提供了形成这种互连结构的方法。该方法很容易扩展到包含多个布线级别的互连结构，并且与双镶嵌后端（BEOL）处理兼容。

10. 发明授权

US06759321B2 Stabilization of fluorine-containing low-k dielectrics in a metal/insulator wiring structure by ultraviolet irradiation 失效
标题翻译：通过紫外线照射使金属/绝缘体布线结构中的含氟低k电介质稳定化
公开(公告)号：US06759321B2
公开(公告)日：2004-07-06
申请号：US10205526
申请日：2002-07-25
申请人： Katherina Babich , Alessandro Callegari , Stephen Alan Cohen , Alfred Grill , Christopher Vincent Jahnes , Vishnubhai Vitthalbhai Patel , Sampath Purushothaman , Katherine Lynn Saenger
发明人： Katherina Babich , Alessandro Callegari , Stephen Alan Cohen , Alfred Grill , Christopher Vincent Jahnes , Vishnubhai Vitthalbhai Patel , Sampath Purushothaman , Katherine Lynn Saenger
IPC分类号： H01L214763
CPC分类号： H01L21/76825 , H01L21/0212 , H01L21/02274 , H01L21/02348 , H01L21/31058 , H01L21/3127 , H01L21/31629 , H01L21/76814 , H01L21/76828 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for providing regions of substantially lower fluorine content in a fluorine containing dielectric is described incorporating exposing a region to ultraviolet radiation and annealing at an elevated temperature to remove partially disrupted fluorine from the region. The invention overcomes the problem of fluorine from a fluorine containing dielectric reacting with other materials while maintaining a bulk dielectric material of sufficiently high or original fluorine content to maintain an effective low dielectric constant in semiconductor chip wiring interconnect structures.
摘要翻译：描述了在含氟电介质中提供基本上较低氟含量的区域的方法，其包括将区域暴露于紫外线辐射并在升高的温度下退火以从该区域去除部分被破坏的氟。本发明克服了与含氟介质与其他材料反应的氟的问题，同时保持足够高或原始氟含量的体电介质材料，以保持半导体芯片布线互连结构中有效的低介电常数。

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