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1. 发明授权

US06570255B2 Method for forming interconnects on semiconductor substrates and structures formed 失效
公开(公告)号：US06570255B2
公开(公告)日：2003-05-27
申请号：US10191015
申请日：2002-07-08
申请人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , John Michael Cotte , Lynne Gignac , Wilma Jean Horkans , Kenneth Parker Rodbell
发明人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , John Michael Cotte , Lynne Gignac , Wilma Jean Horkans , Kenneth Parker Rodbell
IPC分类号： H01L2348
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for forming metal interconnect in a semiconductor structure and the structure formed are disclosed. In the method, a seed layer of a first metal is first deposited into an interconnect opening wherein the seed layer has an average grain size of at least 0.0005 &mgr;m. The semiconductor structure is then annealed at a temperature sufficient to grow the average grain size in the seed layer to at least the film thickness. A filler layer of a second metal is then deposited to fill the interconnect opening overlaying the seed layer such that the filler layer has an average grain size of larger than 0.0005 &mgr;m and comparable to the annealed seed layer.

2. 发明授权

US06429523B1 Method for forming interconnects on semiconductor substrates and structures formed 失效
标题翻译：在半导体衬底上形成互连的方法和形成的结构
公开(公告)号：US06429523B1
公开(公告)日：2002-08-06
申请号：US09755899
申请日：2001-01-04
申请人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , John Michael Cotte , Lynne Gignac , Wilma Jean Horkans , Kenneth Parker Rodbell
发明人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , John Michael Cotte , Lynne Gignac , Wilma Jean Horkans , Kenneth Parker Rodbell
IPC分类号： H01L2348
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for forming metal interconnect in a semiconductor structure and the structure formed are disclosed. In the method, a seed layer of a first metal is first deposited into an interconnect opening wherein the seed layer has an average grain size of at least 0.0005 &mgr;m. The semiconductor structure is then annealed at a temperature sufficient to grow the average grain size in the seed layer to at least the film thickness. A filler layer of a second metal is then deposited to fill the interconnect opening overlaying the seed layer such that the filler layer has an average grain size of larger than 0.0005 &mgr;m and comparable to the annealed seed layer.
摘要翻译：公开了一种在半导体结构中形成金属互连的方法和形成的结构。在该方法中，首先将第一金属的晶种层沉积到互连开口中，其中晶种层的平均晶粒尺寸至少为0.0005μm。然后将半导体结构在足以将种子层中的平均晶粒尺寸生长至至少膜厚度的温度下退火。然后沉积第二金属的填料层以填充覆盖种子层的互连开口，使得填充层的平均粒度大于0.0005μm，并且与退火种子层相当。

3. 发明授权

US06709562B1 Method of making electroplated interconnection structures on integrated circuit chips 有权
标题翻译：在集成电路芯片上制作电镀互连结构的方法
公开(公告)号：US06709562B1
公开(公告)日：2004-03-23
申请号：US09348632
申请日：1999-07-06
申请人： Panayotis Constantinou Andricacos , Hariklia Deligianni , John Owen Dukovic , Daniel Charles Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth Parker Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
发明人： Panayotis Constantinou Andricacos , Hariklia Deligianni , John Owen Dukovic , Daniel Charles Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth Parker Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
IPC分类号： C25D712
CPC分类号： H01L21/2885 , C25D3/38 , C25D7/123 , H01L21/76877
摘要： A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
摘要翻译：描述了用于制造用于集成电路芯片的亚微米互连结构的过程。通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。这种方法在不留下空隙或接缝的情况下超滤特征的能力是独一无二的，优于其他沉积方法。以这种方式使用电镀Cu的结构的电迁移电阻优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

4. 发明授权

US06268291B1 Method for forming electromigration-resistant structures by doping 有权
标题翻译：通过掺杂形成电迁移结构的方法
公开(公告)号：US06268291B1
公开(公告)日：2001-07-31
申请号：US09204185
申请日：1998-12-03
申请人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , Christopher Carr Parks , Kenneth Parker Rodbell , Roger Yen-Luen Tsai
发明人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , Christopher Carr Parks , Kenneth Parker Rodbell , Roger Yen-Luen Tsai
IPC分类号： H01L2100
CPC分类号： H01L21/2885 , H01L21/76843 , H01L21/76855 , H01L21/76858 , H01L21/76859 , H01L21/76864 , H01L21/76873 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L23/53233 , H01L23/53238 , H01L2924/00013 , H01L2924/0002 , H01L2224/29099 , H01L2924/00
摘要： A method for forming a copper conductor in an electronic structure by first depositing a copper composition in a receptacle formed in the electronic structure, and then adding impurities into the copper composition such that its electromigration resistance is improved is disclosed. In the method, the copper composition can be deposited by a variety of techniques such as electroplating, physical vapor deposition and chemical vapor deposition. The impurities which can be implanted include those of C, O, Cl, S and N at a suitable concentration range between about 0.01 ppm by weight and about 1000 ppm by weight. The impurities can be added by three different methods. In the first method, a copper seed layer is first deposited into a receptacle and an ion implantation process is carried out on the seed layer, which is followed by electroplating copper into the receptacle. In the second method, a copper seed layer is first deposited into a receptacle, a copper composition containing impurities is then electrodeposited into the receptacle and the electronic structure is annealed so that impurities diffuse into the copper seed layer. In the third method, a barrier layer is first deposited into a receptacle, dopant ions are then implanted into the barrier layer with a copper seed layer subsequently deposited on top of the barrier layer. An annealing process for the electronic structure is then carried out such that dopant ions diffuse into the copper seed layer. The present invention method may further include the step of ion-implanting at least one element into a surface layer of the copper conductor after the conductor is first planarized. The surface layer may have a thickness between about 30 Å and about 500 Å. At least one element may be selected from Co, Al, Sn, In, Ti and Cr.
摘要翻译：本发明公开了一种在电子结构中形成铜导体的方法，该方法是先将铜组合物沉积在形成于电子结构中的容器中，然后向铜组合物中添加杂质使其电迁移阻力得到改善。在该方法中，铜组合物可以通过各种技术沉积，例如电镀，物理气相沉积和化学气相沉积。可植入的杂质包括C，O，Cl，S和N的杂质，其浓度范围为约0.01ppm至约1000ppm。可以通过三种不同的方法加入杂质。在第一种方法中，首先将铜种子层沉积到容器中，并在种子层上进行离子注入工艺，然后将铜电镀到容器中。在第二种方法中，首先将铜种子层沉积到容器中，然后将含有杂质的铜组合物电沉积到容器中，并且将电子结构退火，使得杂质扩散到铜籽晶层中。在第三种方法中，首先将阻挡层沉积到容器中，然后将掺杂剂离子注入到阻挡层中，随后将铜籽晶层沉积在阻挡层的顶部上。然后进行电子结构的退火处理，使得掺杂剂离子扩散到铜籽晶层中。本发明的方法还可以包括在导体首先平坦化之后将至少一种元素离子注入到铜导体的表面层中的步骤。表面层可以具有在约和之间的厚度。至少一种元素可以选自Co，Al，Sn，In，Ti和Cr。

5. 发明授权

US06589874B2 Method for forming electromigration-resistant structures by doping 有权
标题翻译：通过掺杂形成电迁移结构的方法
公开(公告)号：US06589874B2
公开(公告)日：2003-07-08
申请号：US09915932
申请日：2001-07-26
申请人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , Christopher Carr Parks , Kenneth Parker Rodbell , Roger Yen-Luen Tsai
发明人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , Christopher Carr Parks , Kenneth Parker Rodbell , Roger Yen-Luen Tsai
IPC分类号： H01L2100
CPC分类号： H01L21/76843 , H01L21/2885 , H01L21/76855 , H01L21/76858 , H01L21/76859 , H01L21/76864 , H01L21/76873 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a copper conductor in an electronic structure by first depositing a copper composition in a receptacle formed in the electronic structure, and then adding impurities into the copper composition such that its electromigration resistance is improved. In the method, the copper composition can be deposited by a variety of techniques such as electroplating, physical vapor deposition and chemical vapor deposition. The impurities which can be implanted include those of C, O, Cl, S and N at a suitable concentration range between about 0.01 ppm by weight and about 1000 ppm by weight. The impurities can be added by different methods such as ion implantation, annealing and diffusion.
摘要翻译：一种在电子结构中形成铜导体的方法，首先将铜组合物沉积在形成于电子结构中的插座中，然后将杂质添加到铜组合物中，使得其电迁移阻力得到改善。在该方法中，铜组合物可以通过各种技术沉积，例如电镀，物理气相沉积和化学气相沉积。可植入的杂质包括C，O，Cl，S和N的杂质，其浓度范围为约0.01ppm至约1000ppm。可以通过离子注入，退火和扩散等不同方法添加杂质。

6. 发明授权

US08362600B2 Method and structure to reduce soft error rate susceptibility in semiconductor structures 有权
标题翻译：减少半导体结构中软错误率敏感性的方法和结构
公开(公告)号：US08362600B2
公开(公告)日：2013-01-29
申请号：US12689268
申请日：2010-01-19
申请人： Cyril Cabral, Jr. , Michael S. Gordon , David F. Heidel , Conal Eugene Murray , Kenneth Parker Rodbell , Henry Hong Ki Tang
发明人： Cyril Cabral, Jr. , Michael S. Gordon , David F. Heidel , Conal Eugene Murray , Kenneth Parker Rodbell , Henry Hong Ki Tang
IPC分类号： H01L23/556 , H01L21/60
CPC分类号： H01L23/556 , H01L24/13 , H01L2924/01019 , H01L2924/01025 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01084 , H01L2924/1305 , H01L2924/14 , H01L2924/3025 , H01L2924/00
摘要： A method is disclosed that includes providing a semiconductor substrate having one or more device levels including a number of devices, and forming a number of wiring levels on a top surface of the one or more device levels, wherein one or more of the number of wiring levels includes one or more alpha particle blocking shields situated between at least one of the number of devices and a predetermined first location where a terminal pad will be formed in one of the wiring levels, the one or more alpha particle blocking shields placed at a second location, having one or more widths, and occupying a predetermined number of the wiring levels, sufficient to prevent a predetermined percentage of alpha particles of a selected energy or less expected to be emitted from an alpha particle emitting metallization to be formed adjacent and connected to the terminal pad from reaching the one device.
摘要翻译：公开了一种方法，其包括提供具有包括多个器件的一个或多个器件电平的半导体衬底，以及在所述一个或多个器件级的顶表面上形成多个布线电平，其中所述多个布线中的一个或多个水平包括一个或多个α粒子阻挡屏蔽，位于多个器件中的至少一个与预定的第一位置之间，其中端子焊盘将形成在一个布线层中，一个或多个α粒子阻挡屏蔽放置在第二个位置，具有一个或多个宽度并且占据预定数量的布线水平，足以防止预定百分比的α粒子被选择的能量或预期从发射的α粒子发射的金属化物发射出来邻近并连接到终端垫到达一个设备。

7. 发明申请

US20110175211A1 Method And Structure To Reduce Soft Error Rate Susceptibility In Semiconductor Structures 有权
标题翻译：降低半导体结构中软错误率敏感性的方法和结构
公开(公告)号：US20110175211A1
公开(公告)日：2011-07-21
申请号：US12689268
申请日：2010-01-19
申请人： Cyril Cabral, JR. , Michael S. Gordon , David F. Heidel , Conal Eugene Murray , Kenneth Parker Rodbell , Henry Hong Ki Tang
发明人： Cyril Cabral, JR. , Michael S. Gordon , David F. Heidel , Conal Eugene Murray , Kenneth Parker Rodbell , Henry Hong Ki Tang
IPC分类号： H01L23/556 , H01L21/60 , H01L23/52 , H01L21/56
CPC分类号： H01L23/556 , H01L24/13 , H01L2924/01019 , H01L2924/01025 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01084 , H01L2924/1305 , H01L2924/14 , H01L2924/3025 , H01L2924/00
摘要： A method is disclosed that includes providing a semiconductor substrate having one or more device levels including a number of devices, and forming a number of wiring levels on a top surface of the one or more device levels, wherein one or more of the number of wiring levels includes one or more alpha particle blocking shields situated between at least one of the number of devices and a predetermined first location where a terminal pad will be formed in one of the wiring levels, the one or more alpha particle blocking shields placed at a second location, having one or more widths, and occupying a predetermined number of the wiring levels, sufficient to prevent a predetermined percentage of alpha particles of a selected energy or less expected to be emitted from an alpha particle emitting metallization to be formed adjacent and connected to the terminal pad from reaching the one device.
摘要翻译：公开了一种方法，其包括提供具有包括多个器件的一个或多个器件电平的半导体衬底，以及在所述一个或多个器件级的顶表面上形成多个布线电平，其中所述多个布线中的一个或多个水平包括一个或多个α粒子阻挡屏蔽，位于多个器件中的至少一个与预定的第一位置之间，其中端子焊盘将形成在一个布线层中，一个或多个α粒子阻挡屏蔽放置在第二个位置，具有一个或多个宽度并且占据预定数量的布线水平，足以防止预定百分比的α粒子被选择的能量或预期从发射的α粒子发射的金属化物发射出来邻近并连接到终端垫到达一个设备。

8. 发明申请

US20090039270A1 LARGE-AREA ALPHA-PARTICLE DETECTOR AND METHOD FOR USE 审中-公开
标题翻译：大面积ALPHA颗粒检测器和使用方法
公开(公告)号：US20090039270A1
公开(公告)日：2009-02-12
申请号：US11835475
申请日：2007-08-08
申请人： Cyril Cabral, JR. , Michael S. Gordon , Cristina Plettner , Kenneth Parker Rodbell
发明人： Cyril Cabral, JR. , Michael S. Gordon , Cristina Plettner , Kenneth Parker Rodbell
IPC分类号： G01T1/24
CPC分类号： G01T1/242 , G01T1/244
摘要： A method and detector for detecting particle emissions from a test sample includes positioning a detector over the test sample, wherein the detector includes a plurality of detection units, wherein each detection unit includes a first silicon detector and a barrier layer removably disposed over the first silicon detector. The method includes generating a first current signal in the silicon detector in response to receiving a first particle emitted from an atom of the test sample by the silicon detector of the first detection unit, and responsive to a recoiling daughter nuclide of the atom striking the barrier layer of the first detection unit, the recoiling daughter nuclide resulting from emission of the first particle from the atom, absorbing the recoiling daughter nuclide by the barrier layer of the first detection unit.
摘要翻译：一种用于检测来自测试样品的颗粒发射的方法和检测器，包括：将检测器定位在测试样品上，其中检测器包括多个检测单元，其中每个检测单元包括第一硅检测器和可移除地设置在第一硅上的阻挡层探测器。所述方法包括在所述硅检测器中产生第一电流信号，以响应于由所述第一检测单元的硅检测器接收从所述测试样品的原子发射的第一粒子，并且响应于所述原子撞击所述阻挡层的反弹子弹核子所述第一检测单元的层，由所述原子发射所述第一颗粒产生的所述回缩子核素，通过所述第一检测单元的阻挡层吸收所述回弹子体核素。

9. 发明授权

US06448173B1 Aluminum-based metallization exhibiting reduced electromigration and method therefor 失效
标题翻译：铝基金属化显示出减少的电迁移及其方法
公开(公告)号：US06448173B1
公开(公告)日：2002-09-10
申请号：US09589546
申请日：2000-06-07
申请人： Lawrence Alfred Clevenger , Ronald Gene Filippi , Kenneth Parker Rodbell , Roy Charles Iggulden , Chao-Kun Hu , Lynne Marie Gignac , Stefan Weber , Jeffrey Peter Gambino , Rainer Florian Schnabel
发明人： Lawrence Alfred Clevenger , Ronald Gene Filippi , Kenneth Parker Rodbell , Roy Charles Iggulden , Chao-Kun Hu , Lynne Marie Gignac , Stefan Weber , Jeffrey Peter Gambino , Rainer Florian Schnabel
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A dual damascene process capable of reliably producing aluminum interconnects that exhibit improved electromigration characteristics over aluminum interconnects produced by conventional RIE techniques. In particular, the dual damascene process relies on a PVD-Ti/CVD-TiN barrier layer to produce aluminum lines that exhibit significantly reduced saturation resistance levels and/or suppressed electromigration, particularly in lines longer than 100 micrometers. The electromigration lifetime of the dual damascene aluminum line is strongly dependent on the materials and material fill process conditions. Significantly, deviations in materials and processing can result in electromigration lifetimes inferior to that achieved with aluminum RIE interconnects. In one example, current densities as high as 2.5 MA/cm2 are necessary to induce a statistically relevant number of fails due to electromigration.
摘要翻译：一种能够可靠地生产铝互连的双镶嵌工艺，其通过常规RIE技术生产的铝互连件具有改善的电迁移特性。特别地，双镶嵌工艺依赖于PVD-Ti / CVD-TiN阻挡层以产生显示出显着降低的饱和电阻水平和/或抑制电迁移的铝线，特别是在长于100微米的线中。双镶嵌铝线的电迁移寿命很大程度上取决于材料和材料填充工艺条件。重要的是，材料和加工的偏差可导致电迁移寿命低于铝RIE互连实现的寿命。在一个示例中，高达2.5MA / cm 2的电流密度是诱导由于电迁移引起的统计上相关的失败数量所必需的。

10. 发明授权

US08865556B2 Using fast anneal to form uniform Ni(Pt)Si(Ge) contacts on SiGe layer 有权
标题翻译：使用快速退火在SiGe层上形成均匀的Ni（Pt）Si（Ge）接触
公开(公告)号：US08865556B2
公开(公告)日：2014-10-21
申请号：US13611893
申请日：2012-09-12
申请人： Joseph S. Newbury , Kenneth Parker Rodbell , Zhen Zhang , Yu Zhu
发明人： Joseph S. Newbury , Kenneth Parker Rodbell , Zhen Zhang , Yu Zhu
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/02
CPC分类号： H01L21/28518 , H01L29/45 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.
摘要翻译：提供了不使用盖层形成光滑硅化物的技术。一方面，提供一种FET器件。 FET器件包括在BOX上具有SOI层的SOI晶片和形成在晶片中的至少一个有源区域; 所述至少一个有效区域的一部分上的栅极堆叠，其用作所述装置的通道; 源极和漏极区域，其中该器件的源极和漏极区域包括选自硅和硅锗的半导体材料; 并且硅化物接触到器件的源极和漏极区域，其中在硅化物触点和半导体材料之间存在界面，并且其中界面的界面粗糙度小于约5纳米。

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