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1. 发明授权

US08677303B2 Electromigration compensation system 有权
标题翻译：移民补偿制度
公开(公告)号：US08677303B2
公开(公告)日：2014-03-18
申请号：US12900464
申请日：2010-10-07
申请人： Palkesh Jain , Young-Joon Park
发明人： Palkesh Jain , Young-Joon Park
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/82 , H01L23/528 , H01L2924/0002 , H05K3/0005 , H01L2924/00
摘要： An integrated circuit is described. The integrated circuit, comprising: a central processor; a memory; and an electromigration compensation system associated with a plurality of leads within the integrated circuit, wherein the electromigration compensation system causes the plurality of leads to have interlocking, horizontally tapered ends that substantially reduces electromigration divergence and consequently lead resistance and circuit shorting.
摘要翻译：描述了集成电路。该集成电路包括：中央处理器; 记忆以及与所述集成电路内的多个引线相关联的电迁移补偿系统，其中所述电迁移补偿系统使得所述多个引线具有互锁的水平渐缩的端部，其大大减小了电迁移发散，并因此导致引线电阻和电路短路。

2. 发明授权

US08219953B2 Budgeting electromigration-related reliability among metal paths in the design of a circuit 有权
标题翻译：在电路设计中预算金属通道之间的电迁移相关可靠性
公开(公告)号：US08219953B2
公开(公告)日：2012-07-10
申请号：US12355796
申请日：2009-01-18
申请人： Palkesh Jain , Young-Joon Park , Srikanth Krishnan , Guru Chakrapani Prasad
发明人： Palkesh Jain , Young-Joon Park , Srikanth Krishnan , Guru Chakrapani Prasad
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter value representing a magnitude of excess current flowing in a single direction in each metal path is determined. A desired reliability measure for electromigration (EM) is apportioned among the metal paths based on computed parameter values for the corresponding metal path. A reliability analysis for the circuit is performed based on the apportioning. In an embodiment, metal paths which predominantly carry currents with an average value less than a threshold are excluded from being considered as contributors to EM degradation.
摘要翻译：分配电路的不同金属路径对电迁移（EM）可靠性的不平等贡献。在一个实施例中，确定表示在每个金属路径中沿单个方向流动的过量电流的大小的相应参数值。基于用于相应金属路径的计算参数值，在金属路径中分配用于电迁移（EM）的期望的可靠性度量。基于分配进行电路的可靠性分析。在一个实施例中，主要承载具有小于阈值的平均值的电流的金属路径被排除为被认为是EM降解的贡献者。

3. 发明申请

US20090187869A1 Budgeting Electromigration-Related Reliability Among Metal Paths In The Design Of A Circuit 有权
标题翻译：电路设计中金属路径的电子迁移相关可靠性预算
公开(公告)号：US20090187869A1
公开(公告)日：2009-07-23
申请号：US12355796
申请日：2009-01-18
申请人： Palkesh Jain , Young-Joon Park , Srikanth Krishnan , Guruprasad C
发明人： Palkesh Jain , Young-Joon Park , Srikanth Krishnan , Guruprasad C
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter value representing a magnitude of excess current flowing in a single direction in each metal path is determined. A desired reliability measure for electromigration (EM) is apportioned among the metal paths based on computed parameter values for the corresponding metal path. A reliability analysis for the circuit is performed based on the apportioning. In an embodiment, metal paths which predominantly carry currents with an average value less than a threshold are excluded from being considered as contributors to EM degradation.
摘要翻译：分配电路的不同金属路径对电迁移（EM）可靠性的不平等贡献。在一个实施例中，确定表示在每个金属路径中沿单个方向流动的过量电流的大小的相应参数值。基于用于相应金属路径的计算参数值，在金属路径中分配用于电迁移（EM）的期望的可靠性度量。基于分配进行电路的可靠性分析。在一个实施例中，主要承载具有小于阈值的平均值的电流的金属路径被排除为被认为是EM降解的贡献者。

4. 发明授权

US08255850B2 Fabricating IC with NBTI path delay within timing constraints 有权
标题翻译：在时序约束下制造具有NBTI路径延迟的IC
公开(公告)号：US08255850B2
公开(公告)日：2012-08-28
申请号：US12354796
申请日：2009-01-16
申请人： Palkesh Jain , Arvind Nembili Veeravalli , Ajoy Mandal
发明人： Palkesh Jain , Arvind Nembili Veeravalli , Ajoy Mandal
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031
摘要： According to an aspect of the present invention, statistical timing analysis is applied with respect to a stress degradation that occurs in fabricated integrated circuits (IC) when used for a long duration. The circuit design may be suitably modified to account for the degradations (e.g., those caused by NBTI and CHC for transistors, those caused due to electromigration in case of interconnects). As a result, the fabricated ICs may be less susceptible to such degradations. The features are extended to model complex circuit blocks and also account for different degrees of stress that different circuit blocks are subjected to, in a same age of operation.
摘要翻译：根据本发明的一个方面，对于在长时间使用时在制造的集成电路（IC）中发生的应力劣化，应用统计时序分析。可以适当地修改电路设计以解决劣化（例如，由NBTI和CHC对于晶体管引起的那些，由于在互连的情况下由于电迁移引起的那些）。结果，所制造的IC可能不易受到这种劣化的影响。这些特征被扩展到对复杂电路块的建模，并且在相同的操作年龄中也考虑到不同电路块经受的不同程度的应力。

5. 发明申请

US20090187868A1 DESIGN OF INTEGRATED CIRCUITS LESS SUSCEPTIBLE TO DEGRADATIONS IN TRANSISTORS CAUSED DUE TO OPERATIONAL STRESS 有权
标题翻译：集成电路的设计不足以导致由于操作压力而导致的晶体管中的降解
公开(公告)号：US20090187868A1
公开(公告)日：2009-07-23
申请号：US12354796
申请日：2009-01-16
申请人： Palkesh Jain , Arvind Nembili Veeravalli , Ajoy Mandal
发明人： Palkesh Jain , Arvind Nembili Veeravalli , Ajoy Mandal
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： According to an aspect of the present invention, statistical timing analysis is applied with respect to a stress degradation that occurs in fabricated integrated circuits (IC) when used for a long duration. The circuit design may be suitably modified to account for the degradations (e.g., those caused by NBTI and CHC for transistors, those caused due to electromigration in case of interconnects). As a result, the fabricated ICs may be less susceptible to such degradations. The features are extended to model complex circuit blocks and also account for different degrees of stress that different circuit blocks are subjected to, in a same age of operation.
摘要翻译：根据本发明的一个方面，对于在长时间使用时在制造的集成电路（IC）中发生的应力劣化，应用统计时序分析。可以适当地修改电路设计以解决劣化（例如，由NBTI和CHC对于晶体管引起的那些，由于在互连的情况下由于电迁移引起的那些）。结果，所制造的IC可能不易受到这种劣化的影响。这些特征被扩展到对复杂电路块的建模，并且在相同的操作年龄中也考虑到不同电路块经受的不同程度的应力。

6. 发明申请

US20090187368A1 Burn-In Tests To Produce Fabricated Integrated Circuits With Reduced Variations Due To Process Spread 审中-公开
标题翻译：用于生产由于工艺传播而减少变化的制造集成电路的老化测试
公开(公告)号：US20090187368A1
公开(公告)日：2009-07-23
申请号：US12354794
申请日：2009-01-16
申请人： Palkesh Jain
发明人： Palkesh Jain
IPC分类号： G01R31/26
CPC分类号： G01R31/287 , G01R31/2894
摘要： An aspect of the present invention enables burn-in tests to reduce variations due to process spread in fabricated integrated circuits (IC). Fabricated ICs are classified into multiple categories based on performance characteristics (e.g., operational speed) indicative of the extent of process spread in the ICs. The ICs are subjected to burn-in tests, with the severity of stress parameters applied during a burn-in test being proportional to the performance characteristics. As a result, process spread exhibited by the ICs (post burn-in) is reduced.
摘要翻译：本发明的一个方面使得老化测试能够减少由于制造的集成电路（IC）中的工艺扩展而引起的变化。基于表示IC中的工艺扩展程度的性能特征（例如，操作速度）将制造的IC分类为多个类别。对IC进行老化测试，在老化试验期间施加的应力参数的严重程度与性能特征成比例。结果，IC（后期老化）所展现的工艺扩散减少。

7. 发明申请

US20130161718A1 INTEGRATED CIRCUIT DIE AND METHOD OF MAKING 审中-公开
标题翻译：集成电路及其制造方法
公开(公告)号：US20130161718A1
公开(公告)日：2013-06-27
申请号：US13532558
申请日：2012-06-25
申请人： Palkesh Jain , Anand T. Krishnan
发明人： Palkesh Jain , Anand T. Krishnan
IPC分类号： H01L29/423 , H01L29/40
CPC分类号： H01L22/10 , H01L29/401 , H01L29/4232 , H01L29/42324 , H01L29/42372 , H01L29/78
摘要： Integrated circuit dies and methods of making dies are disclosed. An embodiment of a die includes at least one transistor gate, wherein the gate has an area. A conductor is connected to the gate, and wherein the conductor has an area. The area of the conductor is proportional to the area of the gate raised to a power, wherein the power is a function of the failure rate of the gate.
摘要翻译：公开了集成电路管芯和制造模具的方法。芯片的一个实施例包括至少一个晶体管栅极，其中栅极具有一个区域。导体连接到栅极，并且其中导体具有一个区域。导体的面积与增加到功率的栅极的面积成比例，其中功率是门的故障率的函数。

8. 发明申请

US20130002327A1 BIAS TEMPERATURE INSTABILITY-RESISTANT CIRCUITS 有权
标题翻译：偏温不稳定电路
公开(公告)号：US20130002327A1
公开(公告)日：2013-01-03
申请号：US13493371
申请日：2012-06-11
申请人： Palkesh Jain
发明人： Palkesh Jain
IPC分类号： H03K3/286 , G06F17/50 , H03K17/28
CPC分类号： H03K19/00315
摘要： Standard cells that include transistors subject to aging as a result of BTI-related operating conditions are identified and replaced with BTI-resistant standard cells, for example. The BTI-resistant standard cells are typically functionally equivalent circuits (such as circuits included in standard cells in a design library) and are arranged to ensure that critical transistors are protected (e.g., by either extending recovery times and/or turning the transistor off in response to a critical edge transition).
摘要翻译：例如由BTI相关的操作条件导致包含受老化的晶体管的标准电池进行识别并被BTI抗性的标准电池代替。 BTI抗性标准单元通常是功能等效电路（例如设计库中标准单元中包含的电路），并且被布置为确保关键晶体管被保护（例如，通过延长恢复时间和/或使晶体管关断对临界边缘过渡的响应）。

9. 发明申请

US20120167031A1 METHOD FOR DESIGNING A SEMICONDUCTOR DEVICE BASED ON LEAKAGE CURRENT ESTIMATION 有权
标题翻译：基于泄漏电流估计设计半导体器件的方法
公开(公告)号：US20120167031A1
公开(公告)日：2012-06-28
申请号：US12979393
申请日：2010-12-28
申请人： Palkesh Jain , Ajoy Mandal , Arvind NV , V. Visvanathan
发明人： Palkesh Jain , Ajoy Mandal , Arvind NV , V. Visvanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5036 , G06F2217/78
摘要： A method of designing a semiconductor device includes preparing a first design for a semiconductor device and estimating leakage current for the first design. The method also includes determining a leakage current cumulative distribution function (CDF) for the first design. The method further includes preparing a second design for the semiconductor device based on determination of the leakage current CDF for the first design. Further, the method includes estimating leakage current for the second design. The method also includes determining a leakage current CDF for the second design in accordance to the determination of the leakage current CDF for the first design. Moreover, the method includes selecting one of the first design and the second design based on a comparison of the leakage current CDF for the first design and the leakage CDF for the second design.
摘要翻译：一种设计半导体器件的方法包括制备用于半导体器件的第一设计并估计用于第一设计的漏电流。该方法还包括确定第一设计的泄漏电流累积分布函数（CDF）。该方法还包括基于第一设计的泄漏电流CDF的确定来准备半导体器件的第二设计。此外，该方法包括估计第二设计的漏电流。该方法还包括根据第一设计的泄漏电流CDF的确定来确定第二设计的泄漏电流CDF。此外，该方法包括基于第一设计的泄漏电流CDF和用于第二设计的泄漏CDF的比较来选择第一设计和第二设计之一。

10. 发明授权

US08013635B2 Multi-mode circuit and a method for preventing degradation in the multi-mode circuit 有权
标题翻译：多模式电路以及用于防止多模电路劣化的方法
公开(公告)号：US08013635B2
公开(公告)日：2011-09-06
申请号：US12703793
申请日：2010-02-11
申请人： Palkesh Jain , Nagaraj Savithri , Usha Narasimha
发明人： Palkesh Jain , Nagaraj Savithri , Usha Narasimha
IPC分类号： H03K19/00
CPC分类号： H03K19/00315 , G06F1/10 , H03K5/135 , H03K5/1504
摘要： Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode.
摘要翻译：多模电路（电路）和防止电路劣化的方法。电路包括第一晶体管，其使第一模式中的电路起作用。当电路进入第二模式时，第一晶体管响应于第一信号变为无效，从而防止当电路进入第二模式时第一晶体管的劣化。第二晶体管耦合到第一晶体管。第二晶体管响应于第二信号以产生第三信号。第三晶体管耦合到第二晶体管。当电路进入第二模式时，第三晶体管响应于第三信号变为无效，从而防止当电路进入第二模式时第三晶体管的劣化。

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