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1. 发明授权

US08677303B2 Electromigration compensation system 有权
标题翻译：移民补偿制度
公开(公告)号：US08677303B2
公开(公告)日：2014-03-18
申请号：US12900464
申请日：2010-10-07
申请人： Palkesh Jain , Young-Joon Park
发明人： Palkesh Jain , Young-Joon Park
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/82 , H01L23/528 , H01L2924/0002 , H05K3/0005 , H01L2924/00
摘要： An integrated circuit is described. The integrated circuit, comprising: a central processor; a memory; and an electromigration compensation system associated with a plurality of leads within the integrated circuit, wherein the electromigration compensation system causes the plurality of leads to have interlocking, horizontally tapered ends that substantially reduces electromigration divergence and consequently lead resistance and circuit shorting.
摘要翻译：描述了集成电路。该集成电路包括：中央处理器; 记忆以及与所述集成电路内的多个引线相关联的电迁移补偿系统，其中所述电迁移补偿系统使得所述多个引线具有互锁的水平渐缩的端部，其大大减小了电迁移发散，并因此导致引线电阻和电路短路。

2. 发明授权

US08219953B2 Budgeting electromigration-related reliability among metal paths in the design of a circuit 有权
标题翻译：在电路设计中预算金属通道之间的电迁移相关可靠性
公开(公告)号：US08219953B2
公开(公告)日：2012-07-10
申请号：US12355796
申请日：2009-01-18
申请人： Palkesh Jain , Young-Joon Park , Srikanth Krishnan , Guru Chakrapani Prasad
发明人： Palkesh Jain , Young-Joon Park , Srikanth Krishnan , Guru Chakrapani Prasad
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter value representing a magnitude of excess current flowing in a single direction in each metal path is determined. A desired reliability measure for electromigration (EM) is apportioned among the metal paths based on computed parameter values for the corresponding metal path. A reliability analysis for the circuit is performed based on the apportioning. In an embodiment, metal paths which predominantly carry currents with an average value less than a threshold are excluded from being considered as contributors to EM degradation.
摘要翻译：分配电路的不同金属路径对电迁移（EM）可靠性的不平等贡献。在一个实施例中，确定表示在每个金属路径中沿单个方向流动的过量电流的大小的相应参数值。基于用于相应金属路径的计算参数值，在金属路径中分配用于电迁移（EM）的期望的可靠性度量。基于分配进行电路的可靠性分析。在一个实施例中，主要承载具有小于阈值的平均值的电流的金属路径被排除为被认为是EM降解的贡献者。

3. 发明申请

US20090187869A1 Budgeting Electromigration-Related Reliability Among Metal Paths In The Design Of A Circuit 有权
标题翻译：电路设计中金属路径的电子迁移相关可靠性预算
公开(公告)号：US20090187869A1
公开(公告)日：2009-07-23
申请号：US12355796
申请日：2009-01-18
申请人： Palkesh Jain , Young-Joon Park , Srikanth Krishnan , Guruprasad C
发明人： Palkesh Jain , Young-Joon Park , Srikanth Krishnan , Guruprasad C
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter value representing a magnitude of excess current flowing in a single direction in each metal path is determined. A desired reliability measure for electromigration (EM) is apportioned among the metal paths based on computed parameter values for the corresponding metal path. A reliability analysis for the circuit is performed based on the apportioning. In an embodiment, metal paths which predominantly carry currents with an average value less than a threshold are excluded from being considered as contributors to EM degradation.
摘要翻译：分配电路的不同金属路径对电迁移（EM）可靠性的不平等贡献。在一个实施例中，确定表示在每个金属路径中沿单个方向流动的过量电流的大小的相应参数值。基于用于相应金属路径的计算参数值，在金属路径中分配用于电迁移（EM）的期望的可靠性度量。基于分配进行电路的可靠性分析。在一个实施例中，主要承载具有小于阈值的平均值的电流的金属路径被排除为被认为是EM降解的贡献者。

4. 发明授权

US07566652B2 Electrically inactive via for electromigration reliability improvement 有权
标题翻译：电气非活动通道，用于电迁移可靠性改进
公开(公告)号：US07566652B2
公开(公告)日：2009-07-28
申请号：US11491846
申请日：2006-07-24
申请人： Ki-Don Lee , Young-Joon Park , Ennis Takashi Ogawa
发明人： Ki-Don Lee , Young-Joon Park , Ennis Takashi Ogawa
IPC分类号： H01L21/20
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device 300 includes a metal line 304 formed in a first dielectric layer 302. A capping layer 306 is formed the metal line 304. A second dielectric layer 308 is formed over the first dielectric layer 302 and the metal line 304. A first via 310 is formed in the second dielectric layer 308 and in contact with the metal line 304. A second via 312 is formed in the second dielectric layer 308 and in contact with the metal line 304, and is positioned a distance away from the first via 310. An electrically isolated via 326 is formed in the second dielectric layer 308 and in contact with the metal line 304 and in between the first via 310 and the second via 312. A third dielectric layer 314 is formed over the second dielectric layer 308. First and second trenches 316, 318 are formed in the third dielectric layer 314 and in contact with the first via 310 and the second via 312, respectively. An isolated trench 328 is formed in the third dielectric layer and in contact with the isolated via 326. The isolated via 326 mitigates void formation and/or void migration during operation/conduction with electrons traveling from the first trench 316 to the second trench 318 via the metal line 304.
摘要翻译：半导体器件300包括形成在第一电介质层302中的金属线304.覆盖层306形成为金属线304.第二电介质层308形成在第一电介质层302和金属线304上。第一通孔 310形成在第二电介质层308中并与金属线304接触。第二通孔312形成在第二电介质层308中并与金属线304接触，并且与第一通孔310相距一定距离电绝缘通孔326形成在第二电介质层308中并与金属线304接触并且在第一通孔310和第二通孔312之间。第三电介质层314形成在第二介电层308上。首先并且第二沟槽316,318分别形成在第三电介质层314中并与第一通孔310和第二通孔312接触。隔离沟槽328形成在第三电介质层中并且与隔离通孔326接触。隔离通孔326可减少在从第一沟槽316行进到第二沟槽318的电子的操作/传导过程中的空隙形成和/或空隙迁移金属线304。

5. 发明授权

US06762501B1 Low stress integrated circuit copper interconnect structures 有权
标题翻译：低应力集成电路铜互连结构
公开(公告)号：US06762501B1
公开(公告)日：2004-07-13
申请号：US10412900
申请日：2003-04-14
申请人： Young-Joon Park , Andrew Tae Kim
发明人： Young-Joon Park , Andrew Tae Kim
IPC分类号： H01L2352
CPC分类号： H01L23/53238 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Isolated metal structures (110), (140) are formed adjacent to terminated metal lines (100), (130) that are connect by a via (120). The isolated structures (110), (140) act to suppress the stress created in the terminated metal lines (100), (130) during thermal cycling.
摘要翻译：隔离的金属结构（110），（140）与通过通孔（120）连接的端接金属线（100），（130）相邻形成。隔离结构（110），（140）用于抑制在热循环期间在端接的金属线（100），（130）中产生的应力。

6. 发明授权

US10192968B2 Semiconductor devices having gate structures with skirt regions 有权
公开(公告)号：US10192968B2
公开(公告)日：2019-01-29
申请号：US14988819
申请日：2016-01-06
申请人： Jung-Gun You , Myung-Yoon Um , Young-Joon Park , Jeong-Hyo Lee , Ji-Yong Ha , Jun-Sun Hwang
发明人： Jung-Gun You , Myung-Yoon Um , Young-Joon Park , Jeong-Hyo Lee , Ji-Yong Ha , Jun-Sun Hwang
IPC分类号： H01L29/423 , H01L29/78 , H01L21/28 , H01L29/40 , H01L29/66 , H01L21/762 , H01L21/8234 , H01L29/49
摘要： Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin.

7. 发明授权

US07122466B2 Two step semiconductor manufacturing process for copper interconnects 有权
标题翻译：铜互连的两步半导体制造工艺
公开(公告)号：US07122466B2
公开(公告)日：2006-10-17
申请号：US10628198
申请日：2003-07-28
申请人： Young-Joon Park , Srikanth Krishnan
发明人： Young-Joon Park , Srikanth Krishnan
IPC分类号： H01L21/4763 , C25D15/00
CPC分类号： H01L23/53238 , H01L21/2885 , H01L21/76877 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention is a method of manufacturing copper interconnects 30 on a semiconductor wafer 10 where an electroplating process is used to deposit a first layer of copper grains 30d having an initial grain size and a second layer of copper grains 30e having a different initial grain size.
摘要翻译：本发明的一个实施例是在半导体晶片10上制造铜互连30的方法，其中使用电镀工艺沉积具有初始晶粒尺寸的第一层铜颗粒30d和具有初始晶粒尺寸的第二层铜颗粒30e，不同的初始粒度。

8. 发明授权

US09111779B2 IC resistor formed with integral heatsinking structure 有权
标题翻译：集成电阻形成整体散热结构
公开(公告)号：US09111779B2
公开(公告)日：2015-08-18
申请号：US12537994
申请日：2009-08-07
申请人： Young-Joon Park , Ki-Don Lee
发明人： Young-Joon Park , Ki-Don Lee
IPC分类号： H01L29/00 , H01L27/08 , H01L23/367 , H01L49/02 , H01L27/02
CPC分类号： H01L27/0802 , H01L23/367 , H01L27/0248 , H01L28/20 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A resistor is formed on field oxide with a portion of the resistor body configured to overlap an active region in an integrated circuit (IC) substrate to provide heatsinking for the resistor body. In one embodiment, cooling fingers extend from the resistor body beyond the field oxide to overlap the active region. In another embodiment, minor areas of the resistor body overlap the active region. The resistor body may be formed of polycrystalline silicon (polysilicon), silicided polysilicon, or metal. An oxide having greater thermal conductance than the field oxide is formed between the overlapping parts of the resistor body and the active region.
摘要翻译：电阻器形成在场氧化物上，其中电阻体的一部分构造成与集成电路（IC）衬底中的有源区重叠，以提供电阻体的散热。在一个实施例中，冷却指状物从电阻体延伸超过场氧化物以与有源区重叠。在另一个实施例中，电阻体的次要区域与有源区重叠。电阻体可以由多晶硅（多晶硅），硅化多晶硅或金属形成。在电阻体的重叠部分和有源区域之间形成具有比场氧化物更高的导热性的氧化物。

9. 发明申请

US20090228856A1 VIA-NODE-BASED ELECTROMIGRATION RULE-CHECK METHODOLOGY 有权
标题翻译：通过基于NODE的电磁法检查方法
公开(公告)号：US20090228856A1
公开(公告)日：2009-09-10
申请号：US12041984
申请日：2008-03-04
申请人： Young-Joon Park
发明人： Young-Joon Park
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/82
摘要： A method of method of manufacturing an integrated circuit. The method comprises performing an electromigration reliability rule-check for at least one of via node of an integrated circuit, including: calculating a net effective current density of the via node. Calculating the net effective current density including determining a sum of effective current densities for individual leads that are coupled to the via node. Leads configured to transfer electrons away from said via node are assigned a positive polarity of the effective current density. Leads configured to transfer electrons towards the via node are assigned a negative polarity of the effective current density.
摘要翻译：一种制造集成电路的方法。该方法包括对集成电路的通路节点中的至少一个执行电迁移可靠性规则检查，包括：计算通孔节点的净有效电流密度。计算净有效电流密度，包括确定耦合到通孔节点的各个引线的有效电流密度之和。被配置为将电子传送离开所述通孔节点的引线被分配有效电流密度的正极性。被配置为将电子传递到通孔节点的引线被赋予有效电流密度的负极性。

10. 发明申请

US20060038295A1 Selectively encased surface metal structures in a semiconductor device 有权
标题翻译：在半导体器件中选择性地封装表面金属结构
公开(公告)号：US20060038295A1
公开(公告)日：2006-02-23
申请号：US10924346
申请日：2004-08-23
申请人： Richard Faust , Young-Joon Park
发明人： Richard Faust , Young-Joon Park
IPC分类号： H01L23/52
CPC分类号： H01L23/5227 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides, in one embodiment, An integrated circuit device (100). The integrated circuit device (100) comprises a circuit feature (105) located over a semiconductor substrate (110) and an insulating layer (115) located over the circuit feature (105). A protective overcoat (120) is located over the insulating layer (115) and a metal structure (125) is located over the protective overcoat (120). The metal structure (125) is electrically connected to the circuit feature (105) by an interconnect (130). The metal structure (125) is coated with a conductive encasement (135), the conductive encasement (135) terminating at a perimeter (140) of the metal structure (125). Another embodiment of the invention in a method of manufacturing an integrated circuit device (200).
摘要翻译：本发明在一个实施例中提供一种集成电路装置（100）。集成电路器件（100）包括位于半导体衬底（110）之上的电路特征（105）和位于电路特征（105）之上的绝缘层（115）。保护性外涂层（120）位于绝缘层（115）上方，并且金属结构（125）位于保护外涂层（120）上方。金属结构（125）通过互连（130）电连接到电路特征（105）。金属结构（125）涂覆有导电封套（135），导电封套（135）终止于金属结构（125）的周边（140）。在制造集成电路器件（200）的方法中本发明的另一个实施例。

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