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1. 发明授权

US08013635B2 Multi-mode circuit and a method for preventing degradation in the multi-mode circuit 有权
标题翻译：多模式电路以及用于防止多模电路劣化的方法
公开(公告)号：US08013635B2
公开(公告)日：2011-09-06
申请号：US12703793
申请日：2010-02-11
申请人： Palkesh Jain , Nagaraj Savithri , Usha Narasimha
发明人： Palkesh Jain , Nagaraj Savithri , Usha Narasimha
IPC分类号： H03K19/00
CPC分类号： H03K19/00315 , G06F1/10 , H03K5/135 , H03K5/1504
摘要： Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode.
摘要翻译：多模电路（电路）和防止电路劣化的方法。电路包括第一晶体管，其使第一模式中的电路起作用。当电路进入第二模式时，第一晶体管响应于第一信号变为无效，从而防止当电路进入第二模式时第一晶体管的劣化。第二晶体管耦合到第一晶体管。第二晶体管响应于第二信号以产生第三信号。第三晶体管耦合到第二晶体管。当电路进入第二模式时，第三晶体管响应于第三信号变为无效，从而防止当电路进入第二模式时第三晶体管的劣化。

2. 发明申请

US20110193588A1 MULTI-MODE CIRCUIT AND A METHOD FOR PREVENTING DEGRADATION IN THE MULTI-MODE CIRCUIT 有权
标题翻译：多模式电路和多模电路中防止降级的方法
公开(公告)号：US20110193588A1
公开(公告)日：2011-08-11
申请号：US12703793
申请日：2010-02-11
申请人： Palkesh JAIN , Nagaraj Savithri , Usha Narasimha
发明人： Palkesh JAIN , Nagaraj Savithri , Usha Narasimha
IPC分类号： H03K19/003 , H03K19/096
CPC分类号： H03K19/00315 , G06F1/10 , H03K5/135 , H03K5/1504
摘要： Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first transistor is responsive to a first signal to become inactive when the circuit enters into a second mode, thereby preventing degradation of the first transistor when the circuit enters into the second mode. A second transistor is coupled to the first transistor. The second transistor is responsive to a second signal to generate a third signal. A third transistor is coupled to the second transistor. The third transistor is responsive to the third signal to become inactive when the circuit enters into the second mode, thereby preventing degradation of the third transistor when the circuit enters into the second mode.
摘要翻译：多模电路（电路）和防止电路劣化的方法。电路包括第一晶体管，其使第一模式中的电路起作用。当电路进入第二模式时，第一晶体管响应于第一信号变为无效，从而防止当电路进入第二模式时第一晶体管的劣化。第二晶体管耦合到第一晶体管。第二晶体管响应于第二信号以产生第三信号。第三晶体管耦合到第二晶体管。当电路进入第二模式时，第三晶体管响应于第三信号变为无效，从而防止当电路进入第二模式时第三晶体管的劣化。

3. 发明申请

US20060085776A1 Method for circuit sensitivity driven parasitic extraction 有权
标题翻译：电路灵敏度驱动寄生提取方法
公开(公告)号：US20060085776A1
公开(公告)日：2006-04-20
申请号：US11251722
申请日：2005-10-17
申请人： Usha Narasimha , Anthony Hill , Nagaraj Savithri
发明人： Usha Narasimha , Anthony Hill , Nagaraj Savithri
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5022
摘要： The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at that node is critical. If this timing is critical, method calculates the capacitance at said current node using a highly accurate but computationally intensive model. If this timing is not critical, the method uses a less accurate but less computationally intensive model. The method calculates a signal delay for each mode from the drive strength, calculated capacitance and fan-out. This signal delay is compared to a design goal. This method achieves a better trade-off between timing determination run-time and accuracy. Timing criticality can be determined from one or more of conductor length/area, fan-out, logic depth and timing slack.
摘要翻译：本发明的方法确定集成电路设计的时序。在每个节点，该方法确定该节点处信号传播的时间是否至关重要。如果这个时间是至关重要的，则方法使用高度精确但计算密集型的模型来计算所述当前节点处的电容。如果这个时间并不重要，那么该方法使用的精度较低，而且计算密集程度较低。该方法根据驱动强度，计算出的电容和扇出来计算每个模式的信号延迟。将该信号延迟与设计目标进行比较。该方法在定时运行时间和准确度之间实现更好的权衡。定时关键性可以由一个或多个导体长度/面积，扇出，逻辑深度和时序松弛来确定。

4. 发明授权

US07363604B2 Accurate noise modeling in digital designs 有权
标题翻译：数字设计中的精确噪声建模
公开(公告)号：US07363604B2
公开(公告)日：2008-04-22
申请号：US11240924
申请日：2005-09-30
申请人： Anthony M. Hill , John Apostol , Usha Narasimha
发明人： Anthony M. Hill , John Apostol , Usha Narasimha
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5036
摘要： A novel approach to cross-talk analysis takes effective account of the nature of cross-talk interference. This approach employs conservative assumptions regarding (1) the equivalent output resistance, and (2) the definition of noise immunity for the victim gate. Also, this approach uses signal and noise current metrics in modeling the parameters of the active device elements. This approach provides an expectation of detection and elimination of noise hazards that might otherwise not be undetected.
摘要翻译：串通分析的一种新颖的方法可以有效地说明串扰干扰的性质。这种方法采用了关于（1）等效输出电阻的保守假设，以及（2）受害门的抗噪声的定义。此外，该方法使用信号和噪声电流度量来建模有源器件元件的参数。这种方法提供了检测和消除可能未被发现的噪声危害的期望。

5. 发明授权

US07318208B2 Method for circuit sensitivity driven parasitic extraction 有权
标题翻译：电路灵敏度驱动寄生提取方法
公开(公告)号：US07318208B2
公开(公告)日：2008-01-08
申请号：US11251722
申请日：2005-10-17
申请人： Usha Narasimha , Anthony M. Hill , Nagaraj Narasimh Savithri
发明人： Usha Narasimha , Anthony M. Hill , Nagaraj Narasimh Savithri
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at that node is critical. If this timing is critical, method calculates the capacitance at said current node using a highly accurate but computationally intensive model. If this timing is not critical, the method uses a less accurate but less computationally intensive model. The method calculates a signal delay for each node from the drive strength, calculated capacitance and fan-out. This signal delay is compared to a design goal. This method achieves a better trade-off between timing determination run-time and accuracy. Timing criticality can be determined from one or more of conductor length/area, fan-out, logic depth and timing slack.
摘要翻译：本发明的方法确定集成电路设计的时序。在每个节点，该方法确定该节点处信号传播的时间是否至关重要。如果这个时间是至关重要的，则方法使用高度精确但计算密集型的模型来计算所述当前节点处的电容。如果这个时间并不重要，那么该方法使用的精度较低，而且计算密集程度较低。该方法根据驱动强度，计算电容和扇出来计算每个节点的信号延迟。将该信号延迟与设计目标进行比较。该方法在定时运行时间和准确度之间实现更好的权衡。定时关键性可以由一个或多个导体长度/面积，扇出，逻辑深度和时序松弛来确定。

6. 发明申请

US20070079265A1 Accurate noise modeling in digital designs 有权
标题翻译：数字设计中的精确噪声建模
公开(公告)号：US20070079265A1
公开(公告)日：2007-04-05
申请号：US11240924
申请日：2005-09-30
申请人： Anthony Hill , John Apostol , Usha Narasimha
发明人： Anthony Hill , John Apostol , Usha Narasimha
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A novel approach to cross-talk analysis takes effective account of the nature of cross-talk interference. This approach employs conservative assumptions regarding (1) the equivalent output resistance, and (2) the definition of noise immunity for the victim gate. Also, this approach uses signal and noise current metrics in modeling the parameters of the active device elements. This approach provides an expectation of detection and elimination of noise hazards that might otherwise not be undetected.
摘要翻译：串通分析的一种新颖的方法可以有效地说明串扰干扰的性质。这种方法采用了关于（1）等效输出电阻的保守假设，以及（2）受害门的抗噪声的定义。此外，该方法使用信号和噪声电流度量来建模有源器件元件的参数。这种方法提供了检测和消除可能未被发现的噪声危害的期望。

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