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1. 发明授权

US09196351B2 Device including a plurality of memory banks and a pipeline control circuit configured to execute a command on the plurality of memory banks 有权
标题翻译：包括多个存储体的装置和配置成在多个存储体上执行命令的流水线控制电路
公开(公告)号：US09196351B2
公开(公告)日：2015-11-24
申请号：US14177210
申请日：2014-02-10
申请人： PS4 Luxco S.a.r.l
发明人： Kazuhiko Kajigaya , Tomonori Sekiguchi , Kazuo Ono
IPC分类号： G11C7/00 , G11C11/409 , G11C5/02 , G11C5/06 , G11C7/10 , G11C7/18 , G11C11/4076
CPC分类号： G11C11/409 , G11C5/02 , G11C5/06 , G11C7/1039 , G11C7/18 , G11C11/4076
摘要： A method for carrying out read and write operations in a synchronous memory device having a shared I/O, includes receiving a read command directed to a first internal memory bank during a first timeslot, activating the first internal memory bank to access read data at a read address requested by the read command, receiving a write command directed to a second internal memory bank during a second timeslot later than the first timeslot, determining whether a data collision between the read data for output to the shared I/O with normal read latency and write data to be received on the shared I/O with normal write latency would occur, and receiving the write data on the shared I/O with the normal write latency during a third timeslot later than the second timeslot.
摘要翻译：一种用于在具有共享I / O的同步存储器件中执行读写操作的方法，包括在第一时隙期间接收指向第一内部存储体的读取命令，激活第一内部存储体以访问读取数据读取命令所请求的读取地址，在比第一时隙晚的第二时隙期间接收指向第二内部存储体的写入命令，确定用于输出到具有正常读取延迟的共享I / O的读取数据之间的数据冲突并且将发生在具有正常写入延迟的共享I / O上接收的数据，并且在比第二时隙晚的第三个时隙期间以正常写入延迟在共享I / O上接收写入数据。

2. 发明授权

US08966153B2 Semiconductor memory device and information data processing apparatus including the same 有权
标题翻译：半导体存储器件和包括该半导体存储器件的信息数据处理设备
公开(公告)号：US08966153B2
公开(公告)日：2015-02-24
申请号：US14087818
申请日：2013-11-22
申请人： PS4 Luxco S.a.r.l.
发明人： Kazuhiko Kajigaya
IPC分类号： G06F12/00 , G11C7/10 , G11C11/408
CPC分类号： G11C7/1042 , G11C7/1012 , G11C7/1018 , G11C11/4087
摘要： A semiconductor memory device includes a plural number of data input/output pins, a plural number of banks, in each of which a plural number of the information data is stored, a selector and a control circuit. In a first access mode, the control circuit simultaneously accesses the multiple banks in response to a single read-out command or to a single write-in command from outside. In the first access mode, the selector coordinates a plurality of data input/output pins with the multiple banks in a predetermined relationship.
摘要翻译：半导体存储器件包括多个数据输入/输出引脚，多个存储体中存储多个信息数据的多个存储体，选择器和控制电路。在第一访问模式中，控制电路响应于单个读出命令或从外部单个写入命令同时访问多个存储体。在第一访问模式中，选择器以预定关系与多个存储体协调多个数据输入/输出引脚。

3. 发明授权

US09293190B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US09293190B2
公开(公告)日：2016-03-22
申请号：US14618076
申请日：2015-02-10
申请人： PS4 LUXCO S.A.R.L.
发明人： Kazuhiko Kajigaya
IPC分类号： G11C11/4093 , G11C11/4091 , G11C5/02 , G11C7/08 , G11C7/10 , G11C11/4096
CPC分类号： G11C11/4093 , G11C5/025 , G11C7/08 , G11C7/1051 , G11C7/1069 , G11C11/4091 , G11C11/4096 , G11C2207/005
摘要： A semiconductor includes a plurality of memory cell arrays each of which includes a plurality of memory cells. Bitlines extend in one direction in the memory cell arrays to transfer data stored in the memory cells. Wordlines extend perpendicular to the bitlines in the memory cell arrays to select at least one of the memory cells. Local data lines extend parallel to the wordlines outside of the memory cell arrays and convey signals from bitlines. Global data lines convey signals from the local data lines. The global data lines include a part extending parallel to the wordlines and the part is disposed over another one of the memory cell arrays other than a selected memory cell array.
摘要翻译：半导体包括多个存储单元阵列，每个存储单元阵列包括多个存储单元。位线在存储单元阵列中沿一个方向延伸，以传输存储在存储单元中的数据。字线垂直于存储单元阵列中的位线延伸，以选择至少一个存储单元。本地数据线与存储单元阵列外的字线平行延伸，并从位线传送信号。全局数据线传输来自本地数据线的信号。全局数据线包括平行于字线延伸的部分，并且部分被布置在存储单元阵列之外，而不是所选存储单元阵列。

4. 发明授权

US09093177B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09093177B2
公开(公告)日：2015-07-28
申请号：US13776209
申请日：2013-02-25
申请人： PS4 Luxco S.a.r.l.
发明人： Kazuhiko Kajigaya
IPC分类号： G11C29/00 , G11C29/04
CPC分类号： G11C29/04 , G11C29/80
摘要： A semiconductor memory device comprises: plurality of global bit lines; plurality of sense amplifier circuits each connected to corresponding one of the plurality of global bit lines; plurality of column selection lines each of which is connected to or disconnected from corresponding one of the plurality of sense amplifier circuits according to column address information; and plurality of local bit lines including first local bit line and second local bit line. The first local bit line is connected to or disconnected from corresponding one of the plurality of global bit lines according to first row address information different from column address information. The second local bit line replaces first local bit line when defect is present in first local bit line and is connected to or disconnected from corresponding global bit line according to second row address information different from column address information.
摘要翻译：半导体存储器件包括：多个全局位线; 多个读出放大器电路，各自连接到所述多个全局位线中的相应一个; 多个列选择线，其根据列地址信息连接到多个读出放大器电路中的相应一个读取放大器电路或从其断开; 以及包括第一局部位线和第二局部位线的多个局部位线。根据与列地址信息不同的第一行地址信息，第一本地位线与多个全局位线中的相应一个位线连接或断开。当第一本地位线存在缺陷时，第二本地位线替代第一本地位线，并且根据与列地址信息不同的第二行地址信息连接或断开相应的全局位线。

5. 发明授权

US09171606B2 Semiconductor device having complementary bit line pair 有权
标题翻译：具有互补位线对的半导体器件
公开(公告)号：US09171606B2
公开(公告)日：2015-10-27
申请号：US14272575
申请日：2014-05-08
申请人： PS4 LUXCO S.A.R.L.
发明人： Kazuhiko Kajigaya
IPC分类号： G11C11/4097 , G11C11/4091 , G11C11/4096 , G11C11/4099 , G11C11/4094
CPC分类号： G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4099
摘要： Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are disconnected from the bit lines and the dummy cells are connected to the bit lines, and subsequently the bit lines are equalized by the equalizing circuit. When accessing a selected memory cell, the equalizing circuit is inactivated, a corresponding dummy cell is disconnected from the bit line, and subsequently the selected memory cell is connected to the bit line. Thereafter, the sense amplifier is activated so that potentials of the bit lines are amplified respectively.
摘要翻译：本文公开了一种半导体器件，包括互补的位线对，连接到位线的存储器单元，具有与存储单元相同结构的虚拟单元，差分读出放大器，均衡电位的均衡电路以及控制电路。存储单元与位线断开，并且虚设单元连接到位线，随后位线被均衡电路均衡。当访问所选择的存储单元时，均衡电路被去激活，相应的虚设单元与位线断开，随后所选存储单元连接到位线。此后，感测放大器被激活，使得位线的电位分别被放大。

6. 再颁专利

USRE46110E1 Semiconductor device having single-ended sensing amplifier 有权
公开(公告)号：USRE46110E1
公开(公告)日：2016-08-16
申请号：US13957312
申请日：2013-08-01
申请人： PS4 LUXCO S.A.R.L.
发明人： Kazuhiko Kajigaya
IPC分类号： G11C7/00 , G11C5/14 , G11C11/4091 , G11C7/06
CPC分类号： G11C5/147 , G11C7/067 , G11C11/4091
摘要： A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold voltage value of a MOS transistor that constitutes a sense circuit is monitored, and the monitored threshold voltage value of the MOS transistor is converted through the use of a transfer ratio that is determined based on the capacitance of the information charge accumulating capacitor and the parasitic capacitance of the bit line. The converted voltage value is level-shifted so that the pre-charge voltage of a pre-charge circuit is a pre-set voltage, a current feeding capability is added to the level-shifted voltage value, and the voltage is fed as the pre-charge voltage.

7. 发明申请

US20160099041A1 Semiconductor Device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20160099041A1
公开(公告)日：2016-04-07
申请号：US14967883
申请日：2015-12-14
申请人： PS4 Luxco S.a.r.l.
发明人： Kazuhiko Kajigaya
IPC分类号： G11C11/408
CPC分类号： G11C11/4085 , G11C8/08 , G11C11/4094 , G11C11/4097
摘要： Disclosed herein is a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines, and the device further includes a driver configured to drive a selected one of the word lines from an inactive level to an active and to drive the selected one of the word lines from the active level to an intermediate level at a first rate and from the intermediated level to the inactive level at a second rate. The intermediate level is between the active and inactive levels, and the first rate is greater than the second rate.
摘要翻译：这里公开了一种装置，其包括存储单元阵列，该存储单元阵列包括多个字线，每个与字线相交的多个位线和多个存储单元，每个存储单元均设置在字和位线的相关联的一个相交处，设备还包括驱动器，其被配置为将所选择的一条字线从非活动级别驱动到活动状态，并将所选择的一条字线从所述活动级驱动到中间级，以第一速率和从中间级到无效级别以第二速率。中间级别在活动级别和非活动级别之间，并且第一速率大于第二速率。

8. 发明授权

US09177619B2 Semiconductor device having hierarchical bit line structure 有权
标题翻译：具有分层位线结构的半导体器件
公开(公告)号：US09177619B2
公开(公告)日：2015-11-03
申请号：US13714015
申请日：2012-12-13
申请人： PS4 LUXCO S.A.R.L.
发明人： Kazuhiko Kajigaya
IPC分类号： G11C7/02 , G11C7/06 , G11C11/4091 , G11C11/4097
CPC分类号： G11C7/065 , G11C11/4091 , G11C11/4097 , G11C2207/005
摘要： A semiconductor device is disclosed which comprises first and second local bit lines coupled to a plurality of memory cells arranged in first and second areas, respectively, a differential type local sense amplifier amplifying a voltage difference between the first and second local bit lines, a global bit line arranged in an extending direction of the first and second local bit lines, and first and second switches controlling electrical connections between the first and second local bit lines and the global bit line, respectively.
摘要翻译：公开了一种半导体器件，其包括分别耦合到布置在第一和第二区域中的多个存储单元的第一和第二局部位线，放大第一和第二局部位线之间的电压差的差分型本地读出放大器，位线布置在第一和第二局部位线的延伸方向上，第一和第二开关分别控制第一和第二局部位线与全局位线之间的电连接。

9. 发明授权

US09176553B2 Semiconductor device employing DVFS function 有权
标题翻译：采用DVFS功能的半导体器件
公开(公告)号：US09176553B2
公开(公告)日：2015-11-03
申请号：US13942141
申请日：2013-07-15
申请人： PS4 LUXCO S.A.R.L.
发明人： Kazuhiko Kajigaya , Takamasa Suzuki
IPC分类号： G11C7/00 , G06F1/26 , G06F1/32
CPC分类号： G11C11/4076 , G06F1/26 , G06F1/3275 , G11C11/4091 , G11C11/4096 , Y02D10/13 , Y02D10/14
摘要： Disclosed herein is a device that includes: a memory cell array including a plurality of memory cells, the memory cell array operates on a first internal voltage; a peripheral circuit accessing selected one or ones of the memory cells, the peripheral circuit operates on a second internal voltage; a first internal voltage generation circuit that supplies the first internal voltage to the memory cell array; and a second internal voltage generation circuit that supplies the second internal voltage to the peripheral circuit. The second internal voltage generation circuit sets the second internal voltage to a first voltage value in a first mode, and to a second voltage value that is different from the first voltage value in a second mode. The first internal voltage generation circuit sets the first internal voltage to a third voltage value in both the first and second modes.
摘要翻译：这里公开了一种装置，其包括：包括多个存储单元的存储单元阵列，所述存储单元阵列在第一内部电压上工作; 外围电路访问所选择的一个或多个存储单元，外围电路工作在第二内部电压上; 将第一内部电压提供给存储单元阵列的第一内部电压产生电路; 以及将第二内部电压提供给外围电路的第二内部电压产生电路。第二内部电压产生电路将第二内部电压设置为第一模式中的第一电压值，并将第二内部电压设置为与第二模式中的第一电压值不同的第二电压值。第一内部电压产生电路将第一内部电压设置为第一和第二模式中的第三电压值。

10. 发明授权

US08982608B2 Semiconductor device and data processing system 有权
标题翻译：半导体器件和数据处理系统
公开(公告)号：US08982608B2
公开(公告)日：2015-03-17
申请号：US13864329
申请日：2013-04-17
申请人： PS4 Luxco S.a.r.l.
发明人： Kazuhiko Kajigaya
IPC分类号： G11C11/24 , G11C8/12 , G11C11/404 , G11C11/4091
CPC分类号： G11C11/4094 , G11C8/12 , G11C11/24 , G11C11/404 , G11C11/4091 , G11C2211/4016
摘要： A semiconductor device having a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell, so that the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced.
摘要翻译：一种半导体器件，具有包括电容器和具有浮体结构的选择晶体管的存储单元，连接到选择晶体管的位线，位线控制电路和放大从存储单元读出的信号的读出放大器。位线控制电路在存储单元的非访问周期期间将位线设置为第一电位，然后在存储单元的访问周期期间将位线设置为第二电位，使得数据保持时间可以通过减少存储器单元的数据存储节点处的泄漏电流来延长，使得可以减少用于数据保持的平均消耗电流。

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