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热词
    • 5. 发明授权
    • Sample and hold circuit
    • 采样保持电路
    • US4393318A
    • 1983-07-12
    • US154949
    • 1980-05-30
    • Masayuki TakahashiKunihiko GotoHisami TanakaMichinobu Ohhata
    • Masayuki TakahashiKunihiko GotoHisami TanakaMichinobu Ohhata
    • G11C27/02H03K17/687
    • G11C27/02
    • A sample and hold circuit for holding a sampled voltage, having a first MOS transistor for sampling the input voltage and a holding capacitor for holding the sampled voltage, and further comprising a second MOS transistor. The source and the drain of the second transistor are both connected to the output terminal of the circuit. The gate-source capacitance of the first MOS transistor is the sum of the gate-source and gate-drain capacitances of the second MOS transistor. When a voltage for turning on or off the first MOS transistor is applied to the gate of the first MOS transistor, the second MOS transistor is turned off or on respectively. The effect of this invention is that the sampled voltage can be held constant while turning off the first MOS transistor.
    • 一种用于保持采样电压的采样和保持电路,具有用于对输入电压进行采样的第一MOS晶体管和用于保持采样电压的保持电容器,还包括第二MOS晶体管。 第二晶体管的源极和漏极都连接到电路的输出端子。 第一MOS晶体管的栅极 - 源极电容是第二MOS晶体管的栅极 - 源极和栅极 - 漏极电容的总和。 当将第一MOS晶体管的导通或截止电压施加到第一MOS晶体管的栅极时,第二MOS晶体管分别关断或接通。 本发明的效果是,在关闭第一MOS晶体管的同时,采样电压可以保持恒定。