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1. 发明授权

US4896122A Multiple bandwidth crystal controlled oscillator 失效
标题翻译：多带宽晶体振荡器
公开(公告)号：US4896122A
公开(公告)日：1990-01-23
申请号：US380047
申请日：1989-07-14
申请人： Omid Tahernia , Barry W. Herold , Kenneth R. Burch
发明人： Omid Tahernia , Barry W. Herold , Kenneth R. Burch
IPC分类号： H03B5/32
CPC分类号： H03B5/32 , H03B2200/0046 , H03B2200/008 , H03B2200/0082 , H03B2200/0094
摘要： A dual bandwidth crystal controlled oscillator is described having a first transconductance amplifier providing sufficient gain to maintain oscillation with an oscillator crystal at a minimum current drain. A second transconductance amplifier is provided which can be selectively coupled to the first transconductance amplifier, thereby augmenting the gain of the first transconductance amplifier to provide the capability for rapid oscillator start-up following battery saver operation. The dual bandwidth crystal controlled oscillator can be utilized in conventional oscillator and frequency synthesizer applications.
摘要翻译：描述了双带宽晶体控制振荡器，其具有提供足够增益的第一跨导放大器，以使振荡器晶体保持最小电流消耗的振荡。提供第二跨导放大器，其可以选择性地耦合到第一跨导放大器，从而增加第一跨导放大器的增益，以提供在节电器操作之后的快速振荡器启动的能力。双频带晶振控制振荡器可用于常规振荡器和频率合成器应用。

2. 发明授权

US5128632A Adaptive lock time controller for a frequency synthesizer and method therefor 失效
标题翻译：用于频率合成器的自适应锁定时间控制器及其方法
公开(公告)号：US5128632A
公开(公告)日：1992-07-07
申请号：US700966
申请日：1991-05-16
申请人： Richard A. Erhart , Omid Tahernia , Barry W. Herold
发明人： Richard A. Erhart , Omid Tahernia , Barry W. Herold
IPC分类号： H03L7/089 , H03L7/095 , H03L7/107 , H03L7/199
CPC分类号： H03L7/0898 , H03L7/095 , H03L7/107 , H03L7/199 , Y10S331/02
摘要： An adaptive lock time controller for a phase locked loop having dividers for generating first and second loop timing signals, a phase detector, a voltage controlled oscillator, and a charging circuit for generating at least a first control signal for converging the output frequency to one or more predetermined frequency channels and a second control signal for maintaining the output frequency substantially constant, comprises a synchronization generator, a phase lock detector, and a control signal selector. The synchronization generator is responsive to the phase detector for synchronizing the phase lock detector. The phase lock detector detects phase locked and unlocked conditions by generating a count representative of the phase difference between the first and second loop timing signals. When the count generated exceeds a predetermined count, a phase locked condition exists, otherwise the loop is unlocked. The control signal selector selects the first control signal during the predetermined time interval when the phase unlocked condition is detected, and the second control signal when the phase locked condition is detected.
摘要翻译：一种用于锁相环的自适应锁定时间控制器，具有用于产生第一和第二环路定时信号的分频器，相位检测器，压控振荡器和充电电路，用于产生至少第一控制信号，用于将输出频率收敛到一个或更多的预定频率信道和用于维持输出频率基本恒定的第二控制信号包括同步发生器，锁相检测器和控制信号选择器。同步发生器响应于相位检测器以使相位锁定检测器同步。锁相检测器通过产生表示第一和第二环路定时信号之间的相位差的计数来检测锁相和解锁状态。当产生的计数超过预定计数时，存在锁相条件，否则循环被解锁。控制信号选择器在检测到相位解锁状态的预定时间间隔期间选择第一控制信号，并且在检测到锁相条件时选择第二控制信号。

3. 发明授权

US4991187A High speed prescaler 失效
标题翻译：高速预分频器
公开(公告)号：US4991187A
公开(公告)日：1991-02-05
申请号：US382592
申请日：1989-07-21
申请人： Barry W. Herold , Omid Tahernia
发明人： Barry W. Herold , Omid Tahernia
IPC分类号： H03K23/64 , H03K23/66
CPC分类号： H03K23/667
摘要： An apparatus is described for the dual modulus prescaling of a high frequency signal. The apparatus comprises a dual modulus divider, second divider, synchronization circuit for providing a first modulus control signal to the dual modulus divider, and means for coupling the output of the second divider to the input of the synchronization circuit when a second modulus control signal is in a first state.
摘要翻译：描述了用于高频信号的双模式预分频的装置。该装置包括用于向双模数分配器提供第一模数控制信号的双模数分频器，第二分频器，同步电路，以及当第二模数控制信号是第二模数控制信号时将第二分频器的输出耦合到同步电路的输入的装置处于第一状态。

4. 发明授权

US4953187A High speed prescaler 失效
标题翻译：高速预分频器
公开(公告)号：US4953187A
公开(公告)日：1990-08-28
申请号：US300449
申请日：1989-01-23
申请人： Barry W. Herold , Omid Tahernia
发明人： Barry W. Herold , Omid Tahernia
IPC分类号： H03K23/00 , H03K23/64 , H03K23/66
CPC分类号： H03K23/667
摘要： A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages. When a modulas control signal is low, the prescaler operates as five clocked inverters in series having an output which is fed back to the input of the initial stage. That is, the circuit operates as a five stage clocked ring oscillator wherein only one output changes on each clock edge. When a modulas control signal is high indicating that a divide by four is desired, the counter operates as a five stage ring oscillator for seven clock edges. On the eighth edge, feed forward circuitry forces the last three stages to change states simultaneously.
摘要翻译： 4/5预分频电路的高速CMOS除法包括第一，第二，第三，第四和第五反相器级。当调制控制信号为低时，预分频器作为串联的五个时钟反相器工作，该反相器具有反馈到初始级的输入的输出。也就是说，电路作为五级时钟环形振荡器工作，其中在每个时钟边沿上只有一个输出变化。当模数控制信号为高电平时，表示需要除以4，则计数器作为七级时钟沿的五级环形振荡器工作。在第八个边缘，前馈电路强制最后三个阶段同时改变状态。

5. 发明授权

US4901033A Frequency synthesizer with dynamically programmable frequency range of selected loop bandwith 失效
标题翻译：具有动态可编程频率范围的频率合成器
公开(公告)号：US4901033A
公开(公告)日：1990-02-13
申请号：US345809
申请日：1989-05-01
申请人： Barry W. Herold , Omid Tahernia
发明人： Barry W. Herold , Omid Tahernia
IPC分类号： H03L7/089 , H03L7/107 , H03L7/23
CPC分类号： H03L7/23 , H03L7/107 , H03L7/0898
摘要： A frequency synthesizer which includes at least one phase lock loop operative in a selected loop bandwidth state includes a dynamically programmable control circuit for setting the frequency range of its selected loop bandwidth state. In another aspect, the frequency synthesizer may include a plurality of phase lock loop circuits; and a common bias circuit programmably operative to generate at least one bias signal which is coupled commonly to the plurality of phase lock loop circuits for setting a common frequency range for the loop bandwidth states of all of the phase lock loop circuits. In still another aspect, the frequency synthesizer includes a phase lock loop circuit; and a bias circuit programmably operative to generate at least one bias signal which is coupled to the phase lock loop circuit for setting a reference frequency range of the loop bandwidth states thereof, the phase lock loop circuit being dynamically programmable to vary the frequency range settings of the loop bandwidth states in relation to the reference frequency range set by the bias circuit.
摘要翻译：一种频率合成器，其包括以选定的环路带宽状态工作的至少一个锁相环，包括用于设置其选择的环路带宽状态的频率范围的动态可编程控制电路。另一方面，频率合成器可以包括多个锁相环电路; 以及公共偏置电路，其可编程地用于产生至少一个偏置信号，所述至少一个偏置信号共同耦合到所述多个锁相环电路，用于设置所有锁相环电路的环路带宽状态的公共频率范围。另一方面，频率合成器包括锁相环电路; 以及可编程地用于产生耦合到所述锁相环电路的至少一个偏置信号的偏置电路，用于设置其环路带宽状态的参考频率范围，所述锁相环电路是可动态编程的，以改变频率范围设置环路带宽与由偏置电路设置的参考频率范围有关。

6. 发明授权

US5125107A Diagnostic mode for a frequency synthesizer 失效
标题翻译：频率合成器的诊断模式
公开(公告)号：US5125107A
公开(公告)日：1992-06-23
申请号：US317875
申请日：1989-03-02
申请人： Barry W. Herold , Omid Tahernia
发明人： Barry W. Herold , Omid Tahernia
IPC分类号： H03L7/07 , H03L7/089 , H03L7/183
CPC分类号： H03L7/0891 , H03L7/07 , H03L7/183
摘要： A built in test circuit within a frequency synthesizer for use in selective call radio receivers provides a selectable one of a plurality of internal signals as a test signal for diagnosing the frequency synthesizer's output in real time.
摘要翻译：用于选呼通信无线电接收机的频率合成器内建的测试电路提供多个内部信号中的可选择的一个作为测试信号，用于实时诊断频率合成器的输出。

7. 发明授权

US5058204A Synthesized selective call receiver having variable characteristics 失效
标题翻译：具有可变特性的综合选呼接收机
公开(公告)号：US5058204A
公开(公告)日：1991-10-15
申请号：US551669
申请日：1990-07-13
申请人： Omid Tahernia , Walter L. Davis , Barry W. Herold
发明人： Omid Tahernia , Walter L. Davis , Barry W. Herold
IPC分类号： H03J5/02
CPC分类号： H03J5/0281
摘要： A paging receiver has a synthesizer for governing the receive frequency. The paging receiving further has characteristics which are varied in response to the receive frequency. These characteristics include varying the bandwidth of a loop filter within a phase lock loop within the synthesizer as well as varying the time in which a detector circuit used to extract a DC level from a recovered audio signal is disabled. Furthermore, the bandwidth of the loop filter is varied in response to switching from a first receive frequency to a second receive frequency in order to provide for either a uniform frequency lock time or for a rapid frequency lock time. Furthermore, the time in which the detector circuit is disabled is correspondingly changed.
摘要翻译：寻呼接收机具有用于控制接收频率的合成器。寻呼接收还具有响应于接收频率而变化的特性。这些特征包括改变合成器内的锁相环内的环路滤波器的带宽，以及改变用于从恢复的音频信号提取DC电平的检测器电路被禁用的时间。此外，环路滤波器的带宽响应于从第一接收频率切换到第二接收频率而变化，以提供均匀的频率锁定时间或快速频率锁定时间。此外，检测器电路被禁用的时间相应地改变。

8. 发明授权

US4926141A Frequency synthesizer with improved automatic control of loop bandwidth selection 失效
标题翻译：频率合成器具有改进的环路带宽选择自动控制
公开(公告)号：US4926141A
公开(公告)日：1990-05-15
申请号：US345866
申请日：1989-05-01
申请人： Barry W. Herold , Omid Tahernia
发明人： Barry W. Herold , Omid Tahernia
IPC分类号： H03L7/089 , H03L7/107 , H03L7/183
CPC分类号： H03L7/0898 , H03L7/107 , H03L7/183
摘要： A method of and apparatus for automatically selecting one of first and second loop bandwidth states of a phase lock loop circuit of a frequency synthesizer. The phase lock loop circuit is governed by a reference frequency signal and a feedback frequency signal to adjust the frequency of the synthesized frequency signal to a frequency channel setting. Each of the reference and feedback frequency signals include one phase indication per frequency period. The feedback frequency signal is phase and frequency representative of the synthesized frequency signal. The loop bandwidth of the phase lock loop circuit is automatically switched from the first to the second state based on an initial occurrence of three successive phase indications of a selected one of the reference and feedback frequency signals between successive phase indications of the other, and automatically switched back from the second to the first state based on an initial occurrence of two successive phase indications of the other frequency signal between successive phase indications of the selected frequency signal.
摘要翻译：一种用于自动选择频率合成器的锁相环电路的第一和第二环路带宽状态之一的方法和装置。锁相环电路由参考频率信号和反馈频率信号控制，以将合成频率信号的频率调整到频道设置。每个参考和反馈频率信号包括每个频率周期的一个相位指示。反馈频率信号是代表合成频率信号的相位和频率。基于在另一个的连续相位指示之间的参考和反馈频率信号中所选择的一个的三个连续相位指示的初始出现，自相位锁定环电路的回路带宽从第一状态自动切换到第二状态，并且自动地基于所选频率信号的连续相位指示之间的另一频率信号的两个连续相位指示的初始出现，从第二状态切换回第一状态。

9. 发明授权

US4901036A Frequency synthesizer with an interface controller and buffer memory 失效
标题翻译：具有接口控制器和缓冲存储器的频率合成器
公开(公告)号：US4901036A
公开(公告)日：1990-02-13
申请号：US372997
申请日：1989-06-29
申请人： Barry W. Herold , Omid Tahernia , Walter L. Davis , Mario A. Rivas
发明人： Barry W. Herold , Omid Tahernia , Walter L. Davis , Mario A. Rivas
IPC分类号： H03L7/18 , H03J5/02
CPC分类号： H03J5/0281
摘要： A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.
摘要翻译：具有至少一个可编程表征的锁相环电路的频率合成器包括缓冲存储器和响应于从中央控制器接收的操作代码的接口控制器，用于引导用于在所述至少一个锁相环电路，缓冲存储器和中央控制器。在一个实施例中，数据字在中央控制器和锁相环电路或缓冲存储器之间的传送是根据预先指定的协议进行的，并由中央控制器产生的时钟信号来执行。缓冲存储器与至少一个锁相环电路之间的数据字传输也可以根据预先指定的协议进行串行执行，但也可以由频率合成器产生的内部时钟信号自主地进行控制。

10. 发明授权

US06888573B2 Digital pixel sensor with anti-blooming control 失效
标题翻译：数字像素传感器具有防起霜控制
公开(公告)号：US06888573B2
公开(公告)日：2005-05-03
申请号：US10285250
申请日：2002-10-31
申请人： Barry W. Herold
发明人： Barry W. Herold
IPC分类号： H01L27/148 , H01L29/768 , H04N3/14 , H04N5/359 , H04N5/3745 , H04N9/64
CPC分类号： H04N5/37455 , H04N5/35527
摘要： An anti-blooming charge accumulation pixel using an anti-blooming element coupled to the pixel prevents blooming by ensuring that a voltage of a charge accumulation device of the pixel is always returned to a clamping voltage following comparison events. The anti-blooming element is used to return the voltage across a photodiode to the supply voltage when both a low voltage comparison and a high voltage comparison have occurred. A control block is used to determine an input signal to the anti-blooming element based upon the result of a low voltage comparison and a high voltage comparison. The input signal can be used to drive the anti-blooming element to a desired logic level, thereby causing the voltage across the charge accumulation device to be the clamping voltage. The use of the anti-blooming element eliminates blooming to adjacent pixels, independent of an integration time of the pixel.
摘要翻译：使用耦合到该像素的抗起霜元件的抗起霜电荷累积像素通过确保像素的电荷累积装置的电压在比较事件之后总是返回到钳位电压来防止起霜。当发生低电压比较和高电压比较时，抗起霜元件用于将光电二极管两端的电压返回到电源电压。基于低电压比较和高电压比较的结果，使用控制块来确定到防晕元件的输入信号。输入信号可用于将防晕元件驱动到期望的逻辑电平，从而使电荷累积装置两端的电压成为钳位电压。使用抗起霜元件消除了对相邻像素的喷射，而与像素的积分时间无关。

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