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1. 发明授权

US07960790B2 Self-aligned planar double-gate transistor structure 有权
标题翻译：自对平面双栅晶体管结构
公开(公告)号：US07960790B2
公开(公告)日：2011-06-14
申请号：US12119765
申请日：2008-05-13
申请人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanararyan G. Hegde , Meikei Ieong , Erin Catherine Jones
发明人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanararyan G. Hegde , Meikei Ieong , Erin Catherine Jones
IPC分类号： H01L27/01
CPC分类号： H01L29/78648 , H01L21/0338 , H01L21/2007 , H01L21/26506 , H01L21/26586 , H01L29/42384
摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.
摘要翻译：提供了具有横向排列的前（上）和后门的双栅极晶体管。双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 位于器件层上方的前门热氧化物; 前栅极热氧化物上方的前栅极电极层，并与背栅电极垂直对准; 以及设置在背栅极热氧化物层上方的与第一栅极对称的晶体管体。背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

2. 发明申请

US20080246090A1 SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE 有权
标题翻译：自对准平面双栅晶体管结构
公开(公告)号：US20080246090A1
公开(公告)日：2008-10-09
申请号：US12119765
申请日：2008-05-13
申请人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , MeiKei Ieong , Erin Catherine Jones
发明人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , MeiKei Ieong , Erin Catherine Jones
IPC分类号： H01L27/12
CPC分类号： H01L29/78648 , H01L21/0338 , H01L21/2007 , H01L21/26506 , H01L21/26586 , H01L29/42384
摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.
摘要翻译：提供了具有横向排列的前（上）和后门的双栅极晶体管。双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 位于器件层上方的前门热氧化物; 前栅极热氧化物上方的前栅极电极层，并与背栅电极垂直对准; 以及设置在背栅极热氧化物层上方的与第一栅极对称的晶体管体。背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

3. 发明授权

US07453123B2 Self-aligned planar double-gate transistor structure 有权
标题翻译：自对平面双栅晶体管结构
公开(公告)号：US07453123B2
公开(公告)日：2008-11-18
申请号：US11676030
申请日：2007-02-16
申请人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , Meikei Ieong , Erin Catherine Jones
发明人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , Meikei Ieong , Erin Catherine Jones
IPC分类号： H01L27/01
CPC分类号： H01L29/78648 , H01L21/0338 , H01L21/2007 , H01L21/26506 , H01L21/26586 , H01L29/42384
摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.
摘要翻译：提供了具有横向排列的前（上）和后门的双栅极晶体管。双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 在器件层上方的前栅极热氧化物：位于前栅极热氧化物上方并与背栅电极垂直对准的前栅极电极层; 以及设置在所述背栅极热氧化物层上方的与所述第一栅极对称的晶体管体。背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

4. 发明授权

US07205185B2 Self-aligned planar double-gate process by self-aligned oxidation 有权
标题翻译：自对准平面双栅极工艺通过自对准氧化
公开(公告)号：US07205185B2
公开(公告)日：2007-04-17
申请号：US10663471
申请日：2003-09-15
申请人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , MeiKei Ieong , Erin Catherine Jones
发明人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , MeiKei Ieong , Erin Catherine Jones
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/78648 , H01L21/0338 , H01L21/2007 , H01L21/26506 , H01L21/26586 , H01L29/42384
摘要： A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.
摘要翻译：双栅极晶体管具有通过在前栅极附近形成对称侧壁然后在至少1000度的温度下氧化背栅电极足以缓解应力的时间的方法横向排列的前（上）和后门在该结构中，氧化物从晶体管主体的侧面渗透，以增厚外边缘上的背栅氧化层，留下中心的栅极氧化物的有效厚度，与前栅电极对准。任选地，来自氧化物增强物质的侧面的成角度的植入物鼓励外部注入区域中相对较厚的氧化物，并且跨越晶体管体的氧化物延迟植入阻碍垂直方向上的氧化，从而允许增加氧化的横向范围。

5. 发明授权

US06833569B2 Self-aligned planar double-gate process by amorphization 有权
标题翻译：通过非晶化自对准平面双栅极工艺
公开(公告)号：US06833569B2
公开(公告)日：2004-12-21
申请号：US10328234
申请日：2002-12-23
申请人： Omer H. Dokumaci , Bruce B. Doris , Suryanarayan G. Hegde , Meikei Ieong , Erin C. Jones
发明人： Omer H. Dokumaci , Bruce B. Doris , Suryanarayan G. Hegde , Meikei Ieong , Erin C. Jones
IPC分类号： H01L27148
CPC分类号： H01L29/66916 , H01L29/42316 , H01L29/66772 , H01L29/78603 , H01L29/78648 , H01L29/802
摘要： The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment by creating a carrier-depleted zone in portions of the back gate. The carrier-depleted zone reduces the capacitance between the source/drain regions and the back gate thereby providing a high-performance self-aligned planar double-gate field effect transistor (DGFET). The present invention also provides a planar DGFET having a back gate that is aligned with the front gate. The front to back gate alignment is achieved by providing a carrier-depleted zone in portions of the back gate.
摘要翻译：本发明提供一种用于制造具有与前门对准的背栅的平面DGFET的方法。本发明的方法通过在后门的一部分中产生载流子耗尽区来实现该对准。载流子耗尽区减小了源极/漏极区域和后栅极之间的电容，从而提供了高性能自对准平面双栅极场效应晶体管（DGFET）。本发明还提供一种具有与前门对准的后门的平面DGFET。通过在后门的部分中提供载流子耗尽区来实现前到后栅极对准。

6. 发明授权

US06677646B2 Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS 有权
标题翻译：用于高性能凹槽通道CMOS的一次性反向间隔器工艺的方法和结构
公开(公告)号：US06677646B2
公开(公告)日：2004-01-13
申请号：US10117959
申请日：2002-04-05
申请人： Meikei Ieong , Omer H. Dokumaci , Thomas S. Kanarsky , Victor Ku
发明人： Meikei Ieong , Omer H. Dokumaci , Thomas S. Kanarsky , Victor Ku
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L29/456 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/78618 , H01L29/78621
摘要： A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.
摘要翻译：一种高性能凹陷沟道CMOS器件，包括具有凹陷沟道区域和相邻的延伸注入区域和可选的晕轮植入区域的SOI层; 并且提供存在于SOI层顶上的至少一个栅极区域及其制造方法。邻接的延伸部分和可选的晕轮植入区域具有突然的侧向轮廓并且位于所述栅极区域下方。

7. 发明授权

US07041538B2 Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS 失效
标题翻译：制造用于高性能凹陷通道CMOS的一次性反向间隔器工艺的方法
公开(公告)号：US07041538B2
公开(公告)日：2006-05-09
申请号：US10713971
申请日：2003-11-14
申请人： Meikei Ieong , Omer H. Dokumaci , Thomas S. Kanarsky , Victor Ku
发明人： Meikei Ieong , Omer H. Dokumaci , Thomas S. Kanarsky , Victor Ku
IPC分类号： H01L21/00
CPC分类号： H01L29/78696 , H01L29/456 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/78618 , H01L29/78621
摘要： A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.
摘要翻译：一种高性能凹陷沟道CMOS器件，包括具有凹陷沟道区域和相邻的延伸注入区域和可选的晕轮植入区域的SOI层; 并且提供存在于SOI层顶上的至少一个栅极区域及其制造方法。邻接的延伸部分和可选的晕轮植入区域具有突然的侧向轮廓并且位于所述栅极区域下方。

8. 发明授权

US07271446B2 Ultra-thin channel device with raised source and drain and solid source extension doping 有权
标题翻译：超薄通道器件具有源极和漏极以及固态源极延迟掺杂
公开(公告)号：US07271446B2
公开(公告)日：2007-09-18
申请号：US10916814
申请日：2004-08-12
申请人： Omer H. Dokumaci , Bruce B. Doris
发明人： Omer H. Dokumaci , Bruce B. Doris
IPC分类号： H01L27/01
CPC分类号： H01L29/66772 , H01L21/2255 , H01L29/6656 , H01L29/78621
摘要： The inventive method for forming thin channel MOSFETS comprises: providing a structure including at least a substrate having a layer of semiconducting material atop an insulating layer and a gate region formed atop the layer of semiconducting material; forming a conformal oxide film atop the structure; implanting the conformal oxide film; forming a set of spacers atop the conformal oxide film, said set of sidewall spacers are adjacent to the gate region; removing portions of the oxide film, not protected by the set of spacers to expose a region of the semiconducting material; forming raised source/drain regions on the exposed region of the semiconducting material; implanting the raised source/drain regions with a second dopant impurity to form a second dopant impurity region; and annealing a final structure to provide a thin channel MOSFET.
摘要翻译：用于形成薄沟道MOSFET的本发明的方法包括：提供至少包括在绝缘层顶部具有半导体材料层的衬底和形成在半导体材料层顶上的栅极区域的结构的结构; 在结构顶部形成保形氧化膜; 植入保形氧化膜; 在所述共形氧化物膜的上方形成一组间隔物，所述一组侧壁间隔物邻近所述栅极区; 去除未被所述一组间隔物保护的氧化膜的部分以暴露所述半导体材料的区域; 在所述半导体材料的暴露区域上形成凸起的源极/漏极区域; 用第二掺杂杂质注入凸起的源/漏区以形成第二掺杂杂质区; 并退火最终结构以提供薄沟道MOSFET。

9. 发明授权

US06977194B2 Structure and method to improve channel mobility by gate electrode stress modification 有权
标题翻译：通过栅电极应力改变来提高沟道迁移率的结构和方法
公开(公告)号：US06977194B2
公开(公告)日：2005-12-20
申请号：US10695752
申请日：2003-10-30
申请人： Michael P. Belyansky , Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
发明人： Michael P. Belyansky , Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/336 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/72 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
摘要翻译：在制造包括nFET和pFET的互补金属氧化物半导体（CMOS）场效应晶体管的情况下，通过使栅电极的材料与金属反应来增强或调节载流子迁移率，以产生应力合金（优选CoSi 2Si，NiSi或PdSi）。在nFET和pFET两者的情况下，各合金的固有应力对相应晶体管的沟道产生相反的应力。通过在nFET和pFET合金或硅化物中保持相反的应力，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

10. 发明授权

US06667197B1 Method for differential oxidation rate reduction for n-type and p-type materials 失效
标题翻译： n型和p型材料差示氧化速率降低的方法
公开(公告)号：US06667197B1
公开(公告)日：2003-12-23
申请号：US10314499
申请日：2002-12-06
申请人： Oleg Gluschenkov , Bruce B. Doris , Omer H. Dokumaci
发明人： Oleg Gluschenkov , Bruce B. Doris , Omer H. Dokumaci
IPC分类号： H01L2100
CPC分类号： H01L21/823842 , H01L21/823864
摘要： A method of forming a substantially uniform oxide film over surfaces with different level of doping and/or different dopant type is disclosed. In one aspect, a method for forming a uniform oxide spacer on the sidewalls of heavily doped n- and p-type gates is disclosed. The method includes providing a semiconductor substrate having at least two regions with dissimilar dopant characteristics, optionally heating the substrate; and forming a uniform oxide layer over the at least two regions by exposing the substrate to a gaseous mixture including atomic oxygen.
摘要翻译：公开了在具有不同掺杂水平和/或不同掺杂剂类型的表面上形成基本上均匀的氧化膜的方法。一方面，公开了在重掺杂的n型和p型栅极的侧壁上形成均匀的氧化物间隔物的方法。该方法包括提供具有至少两个具有不同掺杂特性的区域的半导体衬底，可选地加热衬底; 以及通过将所述衬底暴露于包括原子氧的气体混合物，在所述至少两个区域上形成均匀的氧化物层。

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