专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080246090A1 SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE 有权
标题翻译：自对准平面双栅晶体管结构
公开(公告)号：US20080246090A1
公开(公告)日：2008-10-09
申请号：US12119765
申请日：2008-05-13
申请人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , MeiKei Ieong , Erin Catherine Jones
发明人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , MeiKei Ieong , Erin Catherine Jones
IPC分类号： H01L27/12
CPC分类号： H01L29/78648 , H01L21/0338 , H01L21/2007 , H01L21/26506 , H01L21/26586 , H01L29/42384
摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.
摘要翻译：提供了具有横向排列的前（上）和后门的双栅极晶体管。双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 位于器件层上方的前门热氧化物; 前栅极热氧化物上方的前栅极电极层，并与背栅电极垂直对准; 以及设置在背栅极热氧化物层上方的与第一栅极对称的晶体管体。背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

2. 发明授权

US07271446B2 Ultra-thin channel device with raised source and drain and solid source extension doping 有权
标题翻译：超薄通道器件具有源极和漏极以及固态源极延迟掺杂
公开(公告)号：US07271446B2
公开(公告)日：2007-09-18
申请号：US10916814
申请日：2004-08-12
申请人： Omer H. Dokumaci , Bruce B. Doris
发明人： Omer H. Dokumaci , Bruce B. Doris
IPC分类号： H01L27/01
CPC分类号： H01L29/66772 , H01L21/2255 , H01L29/6656 , H01L29/78621
摘要： The inventive method for forming thin channel MOSFETS comprises: providing a structure including at least a substrate having a layer of semiconducting material atop an insulating layer and a gate region formed atop the layer of semiconducting material; forming a conformal oxide film atop the structure; implanting the conformal oxide film; forming a set of spacers atop the conformal oxide film, said set of sidewall spacers are adjacent to the gate region; removing portions of the oxide film, not protected by the set of spacers to expose a region of the semiconducting material; forming raised source/drain regions on the exposed region of the semiconducting material; implanting the raised source/drain regions with a second dopant impurity to form a second dopant impurity region; and annealing a final structure to provide a thin channel MOSFET.
摘要翻译：用于形成薄沟道MOSFET的本发明的方法包括：提供至少包括在绝缘层顶部具有半导体材料层的衬底和形成在半导体材料层顶上的栅极区域的结构的结构; 在结构顶部形成保形氧化膜; 植入保形氧化膜; 在所述共形氧化物膜的上方形成一组间隔物，所述一组侧壁间隔物邻近所述栅极区; 去除未被所述一组间隔物保护的氧化膜的部分以暴露所述半导体材料的区域; 在所述半导体材料的暴露区域上形成凸起的源极/漏极区域; 用第二掺杂杂质注入凸起的源/漏区以形成第二掺杂杂质区; 并退火最终结构以提供薄沟道MOSFET。

3. 发明授权

US06977194B2 Structure and method to improve channel mobility by gate electrode stress modification 有权
标题翻译：通过栅电极应力改变来提高沟道迁移率的结构和方法
公开(公告)号：US06977194B2
公开(公告)日：2005-12-20
申请号：US10695752
申请日：2003-10-30
申请人： Michael P. Belyansky , Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
发明人： Michael P. Belyansky , Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/336 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/72 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
摘要翻译：在制造包括nFET和pFET的互补金属氧化物半导体（CMOS）场效应晶体管的情况下，通过使栅电极的材料与金属反应来增强或调节载流子迁移率，以产生应力合金（优选CoSi 2Si，NiSi或PdSi）。在nFET和pFET两者的情况下，各合金的固有应力对相应晶体管的沟道产生相反的应力。通过在nFET和pFET合金或硅化物中保持相反的应力，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

4. 发明授权

US06667197B1 Method for differential oxidation rate reduction for n-type and p-type materials 失效
标题翻译： n型和p型材料差示氧化速率降低的方法
公开(公告)号：US06667197B1
公开(公告)日：2003-12-23
申请号：US10314499
申请日：2002-12-06
申请人： Oleg Gluschenkov , Bruce B. Doris , Omer H. Dokumaci
发明人： Oleg Gluschenkov , Bruce B. Doris , Omer H. Dokumaci
IPC分类号： H01L2100
CPC分类号： H01L21/823842 , H01L21/823864
摘要： A method of forming a substantially uniform oxide film over surfaces with different level of doping and/or different dopant type is disclosed. In one aspect, a method for forming a uniform oxide spacer on the sidewalls of heavily doped n- and p-type gates is disclosed. The method includes providing a semiconductor substrate having at least two regions with dissimilar dopant characteristics, optionally heating the substrate; and forming a uniform oxide layer over the at least two regions by exposing the substrate to a gaseous mixture including atomic oxygen.
摘要翻译：公开了在具有不同掺杂水平和/或不同掺杂剂类型的表面上形成基本上均匀的氧化膜的方法。一方面，公开了在重掺杂的n型和p型栅极的侧壁上形成均匀的氧化物间隔物的方法。该方法包括提供具有至少两个具有不同掺杂特性的区域的半导体衬底，可选地加热衬底; 以及通过将所述衬底暴露于包括原子氧的气体混合物，在所述至少两个区域上形成均匀的氧化物层。

5. 发明授权

US06645867B2 Structure and method to preserve STI during etching 有权
公开(公告)号：US06645867B2
公开(公告)日：2003-11-11
申请号：US09864974
申请日：2001-05-24
申请人： Omer H. Dokumaci , Bruce B. Doris
发明人： Omer H. Dokumaci , Bruce B. Doris
IPC分类号： H01L21301
CPC分类号： H01L21/31144 , H01L21/3185 , H01L21/76224 , H01L21/76283
摘要： Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising lowering, if necessary, the upper surface of said STI oxide to a level below that of adjacent silicon active areas, depositing a nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, filling said depression with a protective film, and removing said nitride layer from said adjacent active areas.

6. 发明授权

US07262087B2 Dual stressed SOI substrates 有权
公开(公告)号：US07262087B2
公开(公告)日：2007-08-28
申请号：US10905062
申请日：2004-12-14
申请人： Dureseti Chidambarrao , Bruce B. Doris , Oleg Gluschenkov , Omer H. Dokumaci , Huilong Zhu
发明人： Dureseti Chidambarrao , Bruce B. Doris , Oleg Gluschenkov , Omer H. Dokumaci , Huilong Zhu
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7843 , Y10S438/938
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

7. 发明授权

US06878582B2 Low-GIDL MOSFET structure and method for fabrication 失效
公开(公告)号：US06878582B2
公开(公告)日：2005-04-12
申请号：US10876873
申请日：2004-06-25
申请人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
发明人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/28105 , H01L29/66484 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7836 , Y10S257/90
摘要： A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.

8. 发明授权

US06780694B2 MOS transistor 有权
标题翻译： MOS晶体管
公开(公告)号：US06780694B2
公开(公告)日：2004-08-24
申请号：US10338930
申请日：2003-01-08
申请人： Bruce B. Doris , Omer H. Dokumaci , Jack A. Mandelman , Carl J. Radens
发明人： Bruce B. Doris , Omer H. Dokumaci , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21338
CPC分类号： H01L21/28114 , H01L21/26586 , H01L21/82385 , H01L21/823864 , H01L29/42376 , H01L29/665
摘要： A method of fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrode structure having a lower gate top. Form a planarizing layer over the gate dielectric layer leaving the gate top of the lower gate electrode structure exposed. Form an upper gate structure over the lower gate electrode structure to form a T-shaped gate electrode with an exposed lower surface of the upper gate surface and exposed vertical sidewalls of the gate electrode. Remove the planarizing layer. Form source/drain extensions in the substrate protected from the short channel effect. Form sidewall spacers adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewalls of the T-shaped gate electrode. Form source/drain regions in the substrate. Form silicide layers on top of the T-shaped gate electrode and above the source/drain regions.
摘要翻译：制造半导体晶体管器件的方法包括以下步骤。提供其上具有栅极介电层的半导体衬底和形成在栅极电介质层上的下部栅极电极结构，而下部栅电极结构具有较低的栅极顶部。在栅极电介质层上形成平坦化层，离开下部栅电极结构的栅极顶部。在下栅极电极结构上形成上栅极结构，形成具有上栅极表面的暴露下表面和暴露的栅电极垂直侧壁的T形栅电极。取出平坦化层。衬底中形成源/漏极扩展，防止短沟道效应。形成邻近上部栅极的暴露的下表面和T形栅电极的暴露的垂直侧壁的侧壁间隔物。在衬底中形成源/漏区。在T形栅电极的顶部和源极/漏极区之上形成硅化物层。

9. 发明授权

US06764883B1 Amorphous and polycrystalline silicon nanolaminate 有权
公开(公告)号：US06764883B1
公开(公告)日：2004-07-20
申请号：US10338071
申请日：2003-01-07
申请人： Omer H. Dokumaci , Oleg Gluschenkov , Michael Belyanksy , Bruce B. Doris
发明人： Omer H. Dokumaci , Oleg Gluschenkov , Michael Belyanksy , Bruce B. Doris
IPC分类号： H01L2100
CPC分类号： B82Y30/00 , B82Y10/00 , B82Y20/00 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/0332 , H01L21/0337 , H01L31/0352
摘要： A method for forming a uniform layered structure comprising an ultra-thin layer of amorphous silicon and its thermal oxide is disclosed. In one aspect, a method for forming a nanolaminate of silicon oxide on a substrate is disclosed. In another aspect, a method for forming a patterned hard mask on a substrate is disclosed. The patterned hard mask includes a nanolaminate of silicon and silicon oxide. The methods are characterized by the oxidation of an amorphous silicon layer using atomic oxygen.

10. 发明授权

US06566210B2 Method of improving gate activation by employing atomic oxygen enhanced oxidation 失效
标题翻译：通过采用原子氧增强氧化改善浇口活化的方法
公开(公告)号：US06566210B2
公开(公告)日：2003-05-20
申请号：US09905233
申请日：2001-07-13
申请人： Atul C. Ajmera , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
发明人： Atul C. Ajmera , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
IPC分类号： H01L21336
CPC分类号： H01L21/28035 , H01L21/32105 , H01L29/4916
摘要： The present invention provides a method of preparing a Si-based metal-insulator-semiconductor (MIS) transistor which prevents the polycrystalline grains of the gate conductor from getting significantly larger by reducing the thermal budget of the sidewall oxidation process. The thermal budget of the inventive sidewall oxidation process is reduced one or two orders of magnitude over conventional prior art sidewall oxidation processes by utilizing atomic oxygen as the oxidizing ambient. The present invention also provides Si-based MIS transistors having a gate conductor having grain sizes of about 0.1, preferably 0.05, &mgr;m or less.
摘要翻译：本发明提供一种制备Si基金属 - 绝缘体半导体（MIS）晶体管的方法，其通过降低侧壁氧化工艺的热量预算来防止栅极导体的多晶晶粒变得明显更大。通过利用原子氧作为氧化环境，本发明的侧壁氧化过程的热预算比常规现有技术的侧壁氧化过程减少一到两个数量级。本发明还提供具有晶体尺寸为约0.1μm，优选0.05μm或更小的栅极导体的Si基MIS晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式