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1. 发明授权

US06181163B2 FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals 有权
标题翻译： FPGA集成电路具有嵌入式SRAM存储块和用于广播地址和控制信号的互连通道
公开(公告)号：US06181163B2
公开(公告)日：2001-01-30
申请号：US09235351
申请日：1999-01-21
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.
摘要翻译：具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多个嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。每个嵌入式存储块具有用于捕获接收的地址信号的地址端口和用于捕获所提供的控制信号的控制端口。提供互连资源，包括用于以广播或窄播为基础将共享地址和控制信号传送到多个存储器块的存储器控制传送互连信道（MCIC）。

2. 发明授权

US6124730A Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources 失效
标题翻译：用于配置具有可变粒度组件的FPGA以提供对互连资源的时间共享访问的方法
公开(公告)号：US6124730A
公开(公告)日：2000-09-26
申请号：US212022
申请日：1998-12-15
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
IPC分类号： H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17748 , H03K19/1737 , H03K19/17736 , H03K19/17756 , H03K19/1778
摘要： A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg. Pairs or quartets of VGB's may be synthetically combined to efficiently define higher order, N:1 DyMUX's.
摘要翻译：可变格式架构（VGA）用于从原始构建元素（CBE）合成每个给定任务的适当量的动态复用能力。这些可配置构建单元（CBE）中的未使用的组合被重新配置以执行进一步的逻辑功能来代替动态复用功能。每个CBE可以可编程地配置为提供不超过2对1的动态多路复用器（2：1 DyMUX）。然后可以将这种合成的2:1 DyMUX的动态可选输出输出到共享互连线上。 CBE的对可以合成，以有效地定义4：1的DyMUX，每个这样的4：1多路复用器占用可配置的构建块（CBB）结构。 CBB的对可以合成组合，以有效地定义8：1 DyMUX，每个这样合成的8：1多路复用器占据L形VGB结构（可变颗粒块）的垂直或水平延伸的腿部分。然后，VGB的如此配置的腿部分可以将由其8：1 DyMUX选择的信号输出到由VGB支路驱动的共享互连线上。 VGB的对或四重组可以合成组合，以有效地定义高阶N：1 DyMUX。

3. 发明授权

US6097664A Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan 有权
标题翻译：多端口SRAM单元阵列具有多个写入路径，包括用于通过可寻址端口进行写入和通过串行边界扫描
公开(公告)号：US6097664A
公开(公告)日：2000-08-01
申请号：US235356
申请日：1999-01-21
申请人： Bai Nguyen , Bradley A. Sharpe-Geisler , Herman M. Chang , Om P. Agrawal
发明人： Bai Nguyen , Bradley A. Sharpe-Geisler , Herman M. Chang , Om P. Agrawal
IPC分类号： G11C8/16 , G11C8/00
CPC分类号： G11C8/16
摘要： A serial scan chain extends into an array of SRAM cells within a multi-ported memory system for allowing serial introduction of write data into the SRAM cells and serial read-back of the data. Initial data may be pre-loaded into the SRAM cells by way of the serial scan chain before being read parallel-wise in response to read requests submitted through any of multiple, parallel data access ports of the system.
摘要翻译：串行扫描链扩展到多端口存储器系统中的SRAM单元阵列，用于将写入数据串行引入SRAM单元和数据的串行读回。响应于通过系统的多个并行数据访问端口中的任何一个提交的读取请求，初始数据可以通过串行扫描链预先加载到SRAM单元中，然后以并行方式读取。

4. 发明授权

US06204686B1 Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources 有权
标题翻译：用于配置具有可变粒度块和共享逻辑的FPGA的方法，用于将结果输出的对称路由提供给不同方向和可三态互连资源
公开(公告)号：US06204686B1
公开(公告)日：2001-03-20
申请号：US09216662
申请日：1998-12-16
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
IPC分类号： G06F738
CPC分类号： H03K19/17756 , H03K19/17736
摘要： A Variable Grain Architecture (VGA) device includes a shared output component (SOC) that may be used for programmably-routing process result signals onto either or plural ones of differently directed longlines within an FPGA. Plural VGB's make shared use of each SOC to output respective function signals to the longlines. The SOC may be also used for programmably-routing signals (e.g., feedthrough signals) that are selectively acquired from either one of equivalent but differently positioned interconnect channels. Such freedom in routing VGB result signals or feedthrough signals can allow FPGA configuring software to explore a wider range of partitioning, placement and/or routing options for finding optimized implementations in the VGA FPGA device of various, supplied design specifications.
摘要翻译：可变粒度结构（VGA）设备包括共享输出组件（SOC），其可以用于将处理结果信号可编程地路由到FPGA内的不同定向长线中的一个或多个上。多个VGB共享使用每个SOC，以将相应的功能信号输出到延绳。 SOC也可用于可编程地路由选择性地从等效但不同位置的互连通道中的任一个获取的信号（例如，馈通信号）。路由VGB结果信号或馈通信号的这种自由可以允许FPGA配置软件探索更广泛的分区，布局和/或布线选项，以便在各种提供的设计规范的VGA FPGA器件中找到优化的实现。

5. 发明授权

US06163168A Efficient interconnect network for use in FPGA device having variable grain architecture 有权
标题翻译：高效互连网络，用于具有可变粒度架构的FPGA器件
公开(公告)号：US06163168A
公开(公告)日：2000-12-19
申请号：US208203
申请日：1998-12-09
申请人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang
发明人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： A logic array device has an array of plural interconnect resources including plural lines and plural switchbox areas, with an array of plural Variable Grain Blocks (VGB's) interspersed within the array of plural interconnect resources. The array of plural interconnect resources does not regularly include lines of single-length or shorter, and the array of plural interconnect resources does not regularly include switchbox areas that are spaced apart from one another by distances of a single-length or shorter. The single-length corresponds to a traverse of a continuous distance covering approximately one VGB.
摘要翻译：逻辑阵列器件具有多个互连资源的阵列，包括多个线路和多个开关盒区域，多个可变格栅块（VGB）的阵列散布在多个互连资源的阵列内。多个互连资源的阵列不规则地包括单个长度或更短的线，并且多个互连资源的阵列不规则地包括通过单个长度或更短的距离彼此间隔开的开关盒区域。单个长度对应于覆盖大约一个VGB的连续距离的横越。

6. 发明授权

US06154051A Tileable and compact layout for super variable grain blocks within FPGA device 有权
标题翻译： FPGA器件内的超可变晶粒块的平铺紧凑布局
公开(公告)号：US06154051A
公开(公告)日：2000-11-28
申请号：US187689
申请日：1998-11-05
申请人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang , Giap H. Tran
发明人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang , Giap H. Tran
IPC分类号： H01L27/02 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H01L27/0207 , H03K19/1778 , H03K19/17796
摘要： A tileable structure is provided for logic array devices. The tileable structure has a mirror-symmetrical arrangement of sets of logic blocks, common control sections for the logic block sets, surrounding interconnect lines, and switching areas at intersections of the interconnect lines.
摘要翻译：为逻辑阵列器件提供了可瓦片结构。可瓦片结构具有逻辑块集合的逻辑对称布置，用于逻辑块集合的公共控制部分，周围互连线以及互连线的交叉处的交换区域。

7. 发明授权

US06526558B2 Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources 失效
标题翻译：用于配置具有可变粒度块和共享逻辑的FPGA的方法，用于将结果输出的对称路由提供给不同方向和可三态互连资源
公开(公告)号：US06526558B2
公开(公告)日：2003-02-25
申请号：US09733878
申请日：2000-12-08
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
IPC分类号： G06F1750
CPC分类号： H03K19/17756 , H03K19/17736
摘要： A Variable Grain Architecture (VGA) device includes a shared output component (SOC) that may be used for programmably-routing process result signals onto either or plural ones of differently directed longlines within an FPGA. Plural VGB's make shared use of each SOC to output respective function signals to the longlines. The SOC may be also used for programmably-routing signals (e.g., feedthrough signals) that are selectively acquired from either one of equivalent but differently positioned interconnect channels. Such freedom in routing VGB result signals or feedthrough signals can allow FPGA configuring software to explore a wider range of partitioning, placement and/or routing options for finding optimized implementations in the VGA FPGA device of various, supplied design specifications.
摘要翻译：可变粒度结构（VGA）设备包括共享输出组件（SOC），其可以用于将处理结果信号可编程地路由到FPGA内的不同定向长线中的一个或多个上。多个VGB共享使用每个SOC，以将相应的功能信号输出到延绳。 SOC也可用于可编程地路由选择性地从等效但不同位置的互连通道中的任一个获取的信号（例如，馈通信号）。路由VGB结果信号或馈通信号的这种自由可以允许FPGA配置软件探索更广泛的分区，布局和/或布线选项，以便在各种提供的设计规范的VGA FPGA器件中找到优化的实现。

8. 发明授权

US6130551A Synthesis-friendly FPGA architecture with variable length and variable timing interconnect 失效
标题翻译：具有可变长度和可变定时互连的合成友好的FPGA架构
公开(公告)号：US6130551A
公开(公告)日：2000-10-10
申请号：US8762
申请日：1998-01-19
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Giap H. Tran , Bai Nguyen
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Giap H. Tran , Bai Nguyen
IPC分类号： G06F17/50 , H03K19/177 , G06F7/38 , H03K19/173
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/17736 , H03K19/17756 , H03K19/17796
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units is organized with symmetrical and complementary Variable Grain Architecture (VGA) and Variable Length Interconnect Architecture (VLI). Synthesis mapping exploits the diversified and symmetric resources of the VGA and VLI to efficiently pack function development into logic units of matched granularity and to transfer signals between logic units with interconnect lines of minimal length.
摘要翻译：具有多个行和列的逻辑功能单元的现场可编程门阵列器件（FPGA）以对称和互补的可变粒度架构（VGA）和可变长度互连架构（VLI）组织。综合映射利用VGA和VLI的多样化和对称资源，将功能开发有效地集成到匹配粒度的逻辑单元中，并在逻辑单元之间传输信号，并以最小长度的互连线传输信号。

9. 发明授权

US6034544A Programmable input/output block (IOB) in FPGA integrated circuits 失效
标题翻译： FPGA集成电路中的可编程输入/输出模块（IOB）
公开(公告)号：US6034544A
公开(公告)日：2000-03-07
申请号：US995615
申请日：1997-12-22
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/17744
摘要： A Field Programmable Gate Array (FPGA) device includes a plurality of input/output blocks (IOBs) and variable grain blocks (VGBs) An inter-connect network provides routing of signals between the IOBs and VGBs. The VGBs include a plurality of L-organized CBBs (configurable logic blocks) having function-producing resources. The IOBs are arranged along a top, left, bottom and right side of the plurality of VGBs. An IOB includes a 1) delay for timing input signals, 2) a configurable output latch which may be set or reset responsive to control signals, and 3) transistor for controlling a NOR line. The IOB is programmably configured to the inter-connect network which includes vertical and horizontal inter-connect channels comprising adjacent inter-connect lines.
摘要翻译：现场可编程门阵列（FPGA）装置包括多个输入/输出块（IOB）和可变粒子块（VGB）。互连网络提供IOB和VGB之间的信号路由。 VGB包括具有功能生成资源的多个L组织CBB（可配置逻辑块）。 IOB沿着多个VGB的顶部，左侧，底部和右侧布置。 IOB包括1）用于定时输入信号的延迟，2）响应于控制信号可以被设置或复位的可配置输出锁存器，以及3）用于控制NOR线路的晶体管。 IOB可编程地配置到包括相邻连接线之间的垂直和水平互连通道的互连网络。

10. 再颁专利

USRE39510E1 FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections 有权
标题翻译：具有嵌入式sram存储器块的FPGA集成电路，具有注册的地址和数据输入部分
公开(公告)号：USRE39510E1
公开(公告)日：2007-03-13
申请号：US10392751
申请日：2003-03-20
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/17748 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has a registered address port for capturing received address signals in response to further-received, address-validating clock signals. Interconnect resources are provided for conveying the address-validating clock signals to address-changing circuitry so that a next address can be generated safely in conjunction with the capturing by the registered address port of a previous address signal.
摘要翻译：具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多个嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。每个嵌入式存储块具有用于响应于进一步接收的地址确认时钟信号来捕获接收到的地址信号的注册地址端口。提供互连资源用于将地址确认的时钟信号传送到地址改变电路，使得可以结合由先前地址信号的注册地址端口的捕获而安全地生成下一个地址。

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