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1. 发明申请

US20050196952A1 Method for production of a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US20050196952A1
公开(公告)日：2005-09-08
申请号：US11065342
申请日：2005-02-25
申请人： Oliver Genz , Markus Kirchhoff , Stefan Machill , Alexander Reb , Barbara Schmidt , Momtchil Stavrev , Maik Stegeman , Stephan Wege
发明人： Oliver Genz , Markus Kirchhoff , Stefan Machill , Alexander Reb , Barbara Schmidt , Momtchil Stavrev , Maik Stegeman , Stephan Wege
IPC分类号： H01L21/027 , H01L21/033 , H01L21/308 , H01L21/311 , H01L21/4763 , H01L21/768 , H01L21/8234 , H01L21/8244
CPC分类号： H01L21/76811 , H01L21/0276 , H01L21/0332 , H01L21/3081 , H01L21/31144
摘要： A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.
摘要翻译：一种制造半导体结构的方法，包括制备半导体衬底，并在所述半导体衬底的表面上产生下部第一，中间第二和上部第三掩模层。该方法还包括在上部第三掩蔽层中形成至少一个第一窗口，使用用于传送第一窗口的第一窗口构造中间第二掩蔽层，使用用于传送第一窗口的第一窗口构造下部第一掩蔽层，以及扩大第一个窗口形成第二个窗口。该方法还包括：使用第二窗口重建中间第二掩蔽层，使用结构化的下部第三掩蔽层，使用第二窗口重构下部第一掩蔽层，并重构半导体衬底，构建半导体衬底; 使用重组的下三层掩蔽层。

2. 发明授权

US07141507B2 Method for production of a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US07141507B2
公开(公告)日：2006-11-28
申请号：US11065342
申请日：2005-02-25
申请人： Oliver Genz , Markus Kirchhoff , Stephan Machill , Alexander Reb , Barbara Schmidt , Momtchil Stavrev , Maik Stegemann , Stephan Wege
发明人： Oliver Genz , Markus Kirchhoff , Stephan Machill , Alexander Reb , Barbara Schmidt , Momtchil Stavrev , Maik Stegemann , Stephan Wege
IPC分类号： H01L21/302
CPC分类号： H01L21/76811 , H01L21/0276 , H01L21/0332 , H01L21/3081 , H01L21/31144
摘要： A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.
摘要翻译：一种制造半导体结构的方法，包括制备半导体衬底，并在所述半导体衬底的表面上产生下部第一，中间第二和上部第三掩模层。该方法还包括在上部第三掩蔽层中形成至少一个第一窗口，使用用于传送第一窗口的第一窗口构造中间第二掩蔽层，使用用于传送第一窗口的第一窗口构造下部第一掩蔽层，以及扩大第一个窗口形成第二个窗口。该方法还包括：使用第二窗口重建中间第二掩蔽层，使用结构化的下部第三掩蔽层，使用第二窗口重构下部第一掩蔽层，并重构半导体衬底，构建半导体衬底; 使用重组的下三层掩蔽层。

3. 发明授权

US07018781B2 Method for fabricating a contact hole plane in a memory module 失效
标题翻译：用于在存储器模块中制造接触孔平面的方法
公开(公告)号：US07018781B2
公开(公告)日：2006-03-28
申请号：US10811509
申请日：2004-03-29
申请人： Hans-Georg Fröhlich , Oliver Genz , Werner Graf , Stefan Gruss , Matthias Handke , Percy Heger , Lars Heineck , Antje Laessig , Alexander Reb , Kristin Schupke , Momtchil Stavrev , Mirko Vogt
发明人： Hans-Georg Fröhlich , Oliver Genz , Werner Graf , Stefan Gruss , Matthias Handke , Percy Heger , Lars Heineck , Antje Laessig , Alexander Reb , Kristin Schupke , Momtchil Stavrev , Mirko Vogt
IPC分类号： G03F7/00
CPC分类号： H01L27/10888 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/76897 , H01L27/10894
摘要： Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.
摘要翻译：公开了一种在具有选择晶体管的存储单元的布置的存储器模块中制造合同孔平面的方法。可以在生产动态随机存取存储器（DRAM）模块期间利用这些方法。

4. 发明申请

US20050003308A1 Method for fabricating a contact hole plane in a memory module 失效
标题翻译：用于在存储器模块中制造接触孔平面的方法
公开(公告)号：US20050003308A1
公开(公告)日：2005-01-06
申请号：US10811509
申请日：2004-03-29
申请人： Hans-Georg Frohlich , Oliver Genz , Werner Graf , Stefan Gruss , Matthias Handke , Percy Heger , Lars Heineck , Antje Laessig , Alexander Reb , Kristin Schupke , Momtchil Stavrev , Mirko Vogt
发明人： Hans-Georg Frohlich , Oliver Genz , Werner Graf , Stefan Gruss , Matthias Handke , Percy Heger , Lars Heineck , Antje Laessig , Alexander Reb , Kristin Schupke , Momtchil Stavrev , Mirko Vogt
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8242 , G03F7/00
CPC分类号： H01L27/10888 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/76897 , H01L27/10894
摘要： In order to fabricate a contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, on a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on the semiconductor surface, an insulator layer is formed on the semiconductor surface and a sacrificial layer is subsequently formed on the insulator layer, then material plugs are produced on the sacrificial layer for the purpose of defining contact openings between the mutually adjacent gate electrode tracks, the sacrificial layer is etched to form material plugs with the underlying sacrificial layer blocks, after the production of the vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, an essentially planar surface being formed, then the sacrificial layer material is etched out from the vitreous layer and the uncovered insulator material is removed above the contact openings on the semiconductor surface and, finally, the contact opening regions are filled with a conductive material.
摘要翻译：为了在具有选择晶体管的存储单元的布置的存储器模块中制造接触孔平面，在半导体衬底上具有半导体表面上相互邻近的栅极电极轨迹的布置，在半导体上形成绝缘体层表面和牺牲层随后形成在绝缘体层上，然后在牺牲层上产生材料插塞以便限定相互相邻的栅极电极轨道之间的接触开口，牺牲层被蚀刻以形成具有下面牺牲的材料塞在玻璃质层的生产之后，在相邻的栅电极轨道之间的接触开口上方露出牺牲层块，形成基本平坦的表面，然后从玻璃质层蚀刻牺牲层材料，并且未覆盖的绝缘体材料在触点上方移除并且最后，用导电材料填充接触开口区域。

5. 发明授权

US07037777B2 Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding use of the etching mask 失效
标题翻译：在微观结构上制造蚀刻掩模的方法，特别是具有沟槽电容器的半导体结构以及蚀刻掩模的相应应用
公开(公告)号：US07037777B2
公开(公告)日：2006-05-02
申请号：US10801781
申请日：2004-03-16
申请人： Hans-Peter Moll , Momtchil Stavrev , Mirko Vogt , Stephan Wege
发明人： Hans-Peter Moll , Momtchil Stavrev , Mirko Vogt , Stephan Wege
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L21/3081 , H01L27/10867
摘要： Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding uses of the etching mask which allow for extremely thin photoresist layers to be employed.
摘要翻译：用于在微观结构上制造蚀刻掩模的方法，特别是具有沟槽电容器的半导体结构以及允许使用极薄的光致抗蚀剂层的蚀刻掩模的相应用途。

6. 发明申请

US20050245042A1 Fabrication method for a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US20050245042A1
公开(公告)日：2005-11-03
申请号：US11099962
申请日：2005-04-06
申请人： Moritz Haupt , Andreas Klipp , Hans-Peter Sperlich , Momtchil Stavrev , Stephan Wege
发明人： Moritz Haupt , Andreas Klipp , Hans-Peter Sperlich , Momtchil Stavrev , Stephan Wege
IPC分类号： H01L21/3065 , H01L21/762 , H01L21/8234 , H01L21/8242
CPC分类号： H01L21/76232
摘要： The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.
摘要翻译：本发明提供一种半导体结构的制造方法，其具有提供半导体衬底（1）的步骤。在半导体衬底（1）上提供和图案化氮化硅层（3）作为沟槽蚀刻掩模的最顶层; 在第一蚀刻步骤中通过沟槽蚀刻掩模形成沟槽（5）; 在所得结构上保形地沉积由氧化硅制成的衬垫层（10），留下在沟槽（5）中深入的间隙（SP）; 执行V等离子体蚀刻步骤，用于在沟槽（5）中形成线层（10）的V轮廓; 其中所述衬垫层（10）被拉回到所述氮化硅层（3）的顶侧的下方; 蚀刻气体混合物包括C 5 C 8 O 2 O 2，在V等离子体蚀刻步骤中使用惰性气体; C 5 / C 2 O 2的比例（V）在2.5和3.5之间; 并且氧化硅和氮化硅之间的V等离子体蚀刻步骤的选择性为至少10。

7. 发明申请

US20080150141A1 Manufacturing method for an integrated semiconductor structure and corresponding semiconductor structure 审中-公开
标题翻译：集成半导体结构的制造方法和相应的半导体结构
公开(公告)号：US20080150141A1
公开(公告)日：2008-06-26
申请号：US11652255
申请日：2007-01-11
申请人： Werner Graf , Andreas Thies , Marco Lepper , Momtchil Stavrev
发明人： Werner Graf , Andreas Thies , Marco Lepper , Momtchil Stavrev
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5329 , H01L21/76829 , H01L21/76832 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate with a main surface; forming a wiring metal layer above said main surface; forming a doped getter layer on said wiring metal layer; and forming at least one additional wiring metal layer on said doped getter layer. The present invention also provides a corresponding integrated semiconductor structure and a semiconductor memory device.
摘要翻译：本发明提供一种用于集成半导体结构的制造方法，包括以下步骤：提供具有主表面的半导体衬底; 在所述主表面上形成布线金属层; 在所述布线金属层上形成掺杂的吸气剂层; 以及在所述掺杂的吸气剂层上形成至少一个附加的布线金属层。本发明还提供了相应的集成半导体结构和半导体存储器件。

8. 发明申请

US20060003546A1 Gap-filling for isolation 审中-公开
标题翻译：间隙填充隔离
公开(公告)号：US20060003546A1
公开(公告)日：2006-01-05
申请号：US10881717
申请日：2004-06-30
申请人： Andreas Klipp , Momtchil Stavrev , Moritz Haupt
发明人： Andreas Klipp , Momtchil Stavrev , Moritz Haupt
IPC分类号： H01L21/76
CPC分类号： H01L21/76235 , H01L21/76224
摘要： A method of filling high ratio trenches on a substrate is described. First, an oxidizable layer is deposited on the substrate. Thereafter, a trench fill oxide is deposited on the substrate and on the oxidizable layer. Afterwards, the resulting structure is annealed using an oxygen containing gas such that the oxidizable layer is oxidized.
摘要翻译：描述了在衬底上填充高比率沟槽的方法。首先，将可氧化层沉积在基板上。此后，沟槽填充氧化物沉积在衬底和可氧化层上。然后，使用含氧气体使得到的结构退火，使得可氧化层被氧化。

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