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1. 发明授权

US07037777B2 Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding use of the etching mask 失效
标题翻译：在微观结构上制造蚀刻掩模的方法，特别是具有沟槽电容器的半导体结构以及蚀刻掩模的相应应用
公开(公告)号：US07037777B2
公开(公告)日：2006-05-02
申请号：US10801781
申请日：2004-03-16
申请人： Hans-Peter Moll , Momtchil Stavrev , Mirko Vogt , Stephan Wege
发明人： Hans-Peter Moll , Momtchil Stavrev , Mirko Vogt , Stephan Wege
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L21/3081 , H01L27/10867
摘要： Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding uses of the etching mask which allow for extremely thin photoresist layers to be employed.
摘要翻译：用于在微观结构上制造蚀刻掩模的方法，特别是具有沟槽电容器的半导体结构以及允许使用极薄的光致抗蚀剂层的蚀刻掩模的相应用途。

2. 发明授权

US07018781B2 Method for fabricating a contact hole plane in a memory module 失效
标题翻译：用于在存储器模块中制造接触孔平面的方法
公开(公告)号：US07018781B2
公开(公告)日：2006-03-28
申请号：US10811509
申请日：2004-03-29
申请人： Hans-Georg Fröhlich , Oliver Genz , Werner Graf , Stefan Gruss , Matthias Handke , Percy Heger , Lars Heineck , Antje Laessig , Alexander Reb , Kristin Schupke , Momtchil Stavrev , Mirko Vogt
发明人： Hans-Georg Fröhlich , Oliver Genz , Werner Graf , Stefan Gruss , Matthias Handke , Percy Heger , Lars Heineck , Antje Laessig , Alexander Reb , Kristin Schupke , Momtchil Stavrev , Mirko Vogt
IPC分类号： G03F7/00
CPC分类号： H01L27/10888 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/76897 , H01L27/10894
摘要： Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.
摘要翻译：公开了一种在具有选择晶体管的存储单元的布置的存储器模块中制造合同孔平面的方法。可以在生产动态随机存取存储器（DRAM）模块期间利用这些方法。

3. 发明申请

US20050003308A1 Method for fabricating a contact hole plane in a memory module 失效
标题翻译：用于在存储器模块中制造接触孔平面的方法
公开(公告)号：US20050003308A1
公开(公告)日：2005-01-06
申请号：US10811509
申请日：2004-03-29
申请人： Hans-Georg Frohlich , Oliver Genz , Werner Graf , Stefan Gruss , Matthias Handke , Percy Heger , Lars Heineck , Antje Laessig , Alexander Reb , Kristin Schupke , Momtchil Stavrev , Mirko Vogt
发明人： Hans-Georg Frohlich , Oliver Genz , Werner Graf , Stefan Gruss , Matthias Handke , Percy Heger , Lars Heineck , Antje Laessig , Alexander Reb , Kristin Schupke , Momtchil Stavrev , Mirko Vogt
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8242 , G03F7/00
CPC分类号： H01L27/10888 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/76897 , H01L27/10894
摘要： In order to fabricate a contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, on a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on the semiconductor surface, an insulator layer is formed on the semiconductor surface and a sacrificial layer is subsequently formed on the insulator layer, then material plugs are produced on the sacrificial layer for the purpose of defining contact openings between the mutually adjacent gate electrode tracks, the sacrificial layer is etched to form material plugs with the underlying sacrificial layer blocks, after the production of the vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, an essentially planar surface being formed, then the sacrificial layer material is etched out from the vitreous layer and the uncovered insulator material is removed above the contact openings on the semiconductor surface and, finally, the contact opening regions are filled with a conductive material.
摘要翻译：为了在具有选择晶体管的存储单元的布置的存储器模块中制造接触孔平面，在半导体衬底上具有半导体表面上相互邻近的栅极电极轨迹的布置，在半导体上形成绝缘体层表面和牺牲层随后形成在绝缘体层上，然后在牺牲层上产生材料插塞以便限定相互相邻的栅极电极轨道之间的接触开口，牺牲层被蚀刻以形成具有下面牺牲的材料塞在玻璃质层的生产之后，在相邻的栅电极轨道之间的接触开口上方露出牺牲层块，形成基本平坦的表面，然后从玻璃质层蚀刻牺牲层材料，并且未覆盖的绝缘体材料在触点上方移除并且最后，用导电材料填充接触开口区域。

4. 发明申请

US20050148193A1 Photolithographic method for forming a structure in a semiconductor substrate 审中-公开
标题翻译：用于在半导体衬底中形成结构的光刻方法
公开(公告)号：US20050148193A1
公开(公告)日：2005-07-07
申请号：US10496102
申请日：2002-11-14
申请人： Markus Kirchhoff , Mirko Vogt , Stephan Wege , Frank Katzwinkel
发明人： Markus Kirchhoff , Mirko Vogt , Stephan Wege , Frank Katzwinkel
IPC分类号： G03F7/09 , H01L21/027 , H01L21/033 , H01L21/308 , H01L21/31 , H01L21/311 , H01L21/312 , H01L21/3213 , H01L21/762 , H01L21/8242
CPC分类号： H01L21/3081 , H01L21/02115 , H01L21/02274 , H01L21/312
摘要： To form a pattern in a semiconductor substrate, a buffer layer, which is formed as a carbon layer, is produced between a photoresist layer and an antireflective layer, which is formed on the substrate. The pattern is produced in the photoresist layer by means of a lithography step, and then it is transferred to the layers arranged below in a subsequent step.
摘要翻译：为了在半导体衬底中形成图案，在形成在衬底上的光致抗蚀剂层和抗反射层之间产生形成为碳层的缓冲层。通过光刻步骤在光致抗蚀剂层中产生图案，然后将其转移到随后的步骤中布置在下面的层中。

5. 发明申请

US20050112506A1 Photolithographic patterning process using a carbon hard mask layer of diamond-like hardness produced by a plasma-enhanced deposition process 有权
标题翻译：使用通过等离子体增强沉积工艺生产的类金刚石硬度的碳硬掩模层的光刻图案化工艺
公开(公告)号：US20050112506A1
公开(公告)日：2005-05-26
申请号：US10494063
申请日：2002-10-29
申请人： Gunter Czech , Carsten Fuelber , Marcus Kirchhoff , Maik Stegemann , Mirko Vogt , Stephan Wege
发明人： Gunter Czech , Carsten Fuelber , Marcus Kirchhoff , Maik Stegemann , Mirko Vogt , Stephan Wege
IPC分类号： G03F7/36 , H01L21/033 , H01L21/308 , H01L21/311 , H01L21/314
CPC分类号： H01L21/3146 , H01L21/0332 , H01L21/3081 , H01L21/31144
摘要： A carbon hard mask layer is applied to a substrate to be patterned by means of a plasma-enhanced deposition process in such a manner that it has a hardness comparable to that of diamond in at least one layer thickness section. During the production of this diamond-like layer thickness section, the parameters used in the deposition are set in such a manner that growth regions which are produced in a form other than diamond-like are removed again in situ by means of subsequent etching processes and that diamond-like regions which are formed are retained.
摘要翻译：通过等离子体增强沉积工艺将碳硬掩模层施加到待图案化的基板上，使得其具有与至少一层厚度部分中的金刚石相当的硬度。在制造这种类金刚石层厚度部分期间，沉积中使用的参数设置成使得以类似金刚石的形式生产的生长区域通过随后的蚀刻工艺再次原位除去，形成的菱形区域被保留。

6. 发明申请

US20090166318A1 Method of Fabricating an Integrated Circuit 审中-公开
标题翻译：制造集成电路的方法
公开(公告)号：US20090166318A1
公开(公告)日：2009-07-02
申请号：US11966975
申请日：2007-12-28
申请人： Mihel Seitz , Stephan Wege , Mirko Vogt , Juergen Voelkel
发明人： Mihel Seitz , Stephan Wege , Mirko Vogt , Juergen Voelkel
IPC分类号： H01B13/00 , H01L21/306 , B32B3/00
CPC分类号： H01L21/0332 , Y10T428/24355
摘要： A method of fabricating an integrated circuit includes providing a hard mask that includes at least one first layer and one second layer. An etching step is patterned using the hard mask, and a removal step is performed using an etchant in order to at least partially remove the first layer. The first layer and the second layer are configured in such a way that the first layer is etched by the etchant with a higher etch rate than the second layer.
摘要翻译：一种制造集成电路的方法包括提供包括至少一个第一层和一层第二层的硬掩模。使用硬掩模对蚀刻步骤进行图案化，并且使用蚀刻剂进行去除步骤，以便至少部分地去除第一层。第一层和第二层被配置成使得第一层被蚀刻剂以比第二层更高的蚀刻速率蚀刻。

7. 发明授权

US07368390B2 Photolithographic patterning process using a carbon hard mask layer of diamond-like hardness produced by a plasma-enhanced deposition process 有权
标题翻译：使用通过等离子体增强沉积工艺生产的类金刚石硬度的碳硬掩模层的光刻图案化工艺
公开(公告)号：US07368390B2
公开(公告)日：2008-05-06
申请号：US10494063
申请日：2002-10-29
申请人： Guenther Czech , Carsten Fuelber , Markus Kirchhoff , Maik Stegemann , Mirko Vogt , Stephan Wege
发明人： Guenther Czech , Carsten Fuelber , Markus Kirchhoff , Maik Stegemann , Mirko Vogt , Stephan Wege
IPC分类号： H01L21/311
CPC分类号： H01L21/3146 , H01L21/0332 , H01L21/3081 , H01L21/31144
摘要： A carbon hard mask layer is applied to a substrate to be patterned by means of a plasma-enhanced deposition process in such a manner that it has a hardness comparable to that of diamond in at least one layer thickness section. During the production of this diamond-like layer thickness section, the parameters used in the deposition are set in such a manner that growth regions which are produced in a form other than diamond-like are removed again in situ by means of subsequent etching processes and that diamond-like regions which are formed are retained.
摘要翻译：通过等离子体增强沉积工艺将碳硬掩模层施加到待图案化的基板上，使得其具有与至少一层厚度部分中的金刚石相当的硬度。在制造这种类金刚石层厚度部分期间，沉积中使用的参数设置成使得以类似金刚石的形式生产的生长区域通过随后的蚀刻工艺再次原位除去，形成的菱形区域被保留。

8. 发明申请

US20080150136A1 Integrated circuit having a metal element 失效
标题翻译：具有金属元件的集成电路
公开(公告)号：US20080150136A1
公开(公告)日：2008-06-26
申请号：US11644285
申请日：2006-12-22
申请人： Mirko Vogt , Yung-Chang Wang , Stephan Hartmann
发明人： Mirko Vogt , Yung-Chang Wang , Stephan Hartmann
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L21/32139
摘要： An integrated circuit is disclosed. The integrated circuit includes a substrate, a metal element, the metal element being arranged on the substrate and including a metal material. A composite element is located over to the metal element, the composite element including the metal material and an additive material.
摘要翻译：公开了一种集成电路。集成电路包括基板，金属元件，金属元件布置在基板上并且包括金属材料。复合元件位于金属元件上方，复合元件包括金属材料和添加剂材料。

9. 发明申请

US20060084236A1 Plasma-enhanced chemical vapour deposition process for depositing silicon nitride or silicon oxynitride, process for producing one such layer arrangement, and layer arrangement 有权
标题翻译：用于沉积氮化硅或氮氧化硅的等离子体增强化学气相沉积工艺，用于生产一种这样的层布置的方法和层布置
公开(公告)号：US20060084236A1
公开(公告)日：2006-04-20
申请号：US10515611
申请日：2003-05-14
申请人： Mirko Vogt
发明人： Mirko Vogt
IPC分类号： H01L21/20
CPC分类号： H01L21/3185 , C23C16/308 , C23C16/345 , H01L28/40
摘要： A plasma-enhanced chemical vapor deposition process for depositing relatively high dielectric constant silicon nitride or oxynitride to form an MIM capacitor is described. The flow rate ratios for the silicon nitride layer are: silane-to-ammonia between 1:20 and 6:5 and silane-to-nitrogen flow between 1:40 and 3:5. A pressure in the process chamber is between 260 Pa and 530 Pa. The flow rate ratios for the silicon oxynitride layer are: silane-to-dinitrogen monoxide between 1:2 and 25:4 and silane-to-nitrogen between 1:100 and 1:10. A larger, non-stoichiometric amount of silicon is incorporated in the layers as the flow rate of the silicon precursor is increased. The layers are deposited in substeps in which the deposition is interrupted between successive substeps. The layer is exposed to an oxygen-containing plasma such that electrically conductive regions of the layer are converted into electrically insulating regions as a result of interaction with the plasma.
摘要翻译：描述了用于沉积相对高的介电常数氮化硅或氮氧化物以形成MIM电容器的等离子体增强化学气相沉积工艺。氮化硅层的流速比为：硅烷与氨在1:20和6:5之间，硅烷与氮的流量在1:40与3:5之间。处理室中的压力在260Pa和530Pa之间。氮氧化硅层的流速比为：硅烷与二氧化氮在1:2和25:4之间，硅烷与氮之间在1:100和 1:10 随着硅前体的流速增加，更多的非化学计量的硅被并入层中。这些层以子步骤沉积，其中沉积在连续的子步骤之间中断。该层暴露于含氧等离子体，使得该层的导电区域由于与等离子体的相互作用而被转换成电绝缘区域。

10. 发明授权

US07538034B2 Integrated circuit having a metal element 失效
标题翻译：具有金属元件的集成电路
公开(公告)号：US07538034B2
公开(公告)日：2009-05-26
申请号：US11644285
申请日：2006-12-22
申请人： Mirko Vogt , Yung-Chang Wang , Stephan Hartmann
发明人： Mirko Vogt , Yung-Chang Wang , Stephan Hartmann
IPC分类号： H01L21/44
CPC分类号： H01L21/32139
摘要： An integrated circuit is disclosed. The integrated circuit includes a substrate, a metal element, the metal element being arranged on the substrate and including a metal material. A composite element is located over to the metal element, the composite element including the metal material and an additive material.
摘要翻译：公开了一种集成电路。集成电路包括基板，金属元件，金属元件布置在基板上并且包括金属材料。复合元件位于金属元件上方，复合元件包括金属材料和添加剂材料。

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