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1. 发明授权

US07331004B1 Data storage system analyzer having self reset 有权
标题翻译：数据存储系统分析仪具有自动复位功能
公开(公告)号：US07331004B1
公开(公告)日：2008-02-12
申请号：US10812580
申请日：2004-03-30
申请人： Ofer Porat , Alexander Rabinovich , Tony Phelan
发明人： Ofer Porat , Alexander Rabinovich , Tony Phelan
IPC分类号： G01R31/28 , H04B3/46 , H03M9/00
CPC分类号： H04B3/46
摘要： A transmitter board transmits a copy of signals in a system being analyzed by the system analyzer. The copy of such signals comprises serial data in a low byte serial link and in a high byte serial link. The signals include special characters interspersed in a pattern with the data in the low and high byte serial links. An analyzer board includes a serializer-deserializer for receiving the transmitted serial data when the analyzer board is plugged into the transmitter board for converting the received data and the interspersed special characters in both the low and high byte serial links into corresponding data and interspersed special characters in low byte and high byte parallel links. A mismatch between the data and the interspersed pattern of special characters in the converted low byte parallel link and the pattern of special characters in the converted high byte parallel links resets the serializer-deserializer.
摘要翻译：发射机板在由系统分析仪分析的系统中传输信号的副本。这种信号的副本包括低字节串行链路和高字节串行链路中的串行数据。这些信号包括散布在低字节和高字节串行链路中的数据的特殊字符。分析器板包括串行器 - 解串器，用于当分析器板插入发射机板用于将接收到的数据和低字节和高字节串行链路中散布的特殊字符插入到发送器板中时，用于接收所发送的串行数据，使其对应的数据和散布的特殊字符在低字节和高字节并行链路中。数据与转换的低字节并行链接中的特殊字符的散布图案之间的不匹配以及转换的高字节并行链接中的特殊字符的模式会重置串行器 - 解串器。

2. 发明授权

US07165196B1 Method for testing serializers/de-serializers 有权
标题翻译：串行器/解串器测试方法
公开(公告)号：US07165196B1
公开(公告)日：2007-01-16
申请号：US10934874
申请日：2004-09-03
申请人： Ofer Porat , Jinhua Chen , Marlon Ramroopsingh , Alexander Rabinovich
发明人： Ofer Porat , Jinhua Chen , Marlon Ramroopsingh , Alexander Rabinovich
IPC分类号： G01R31/28
CPC分类号： G01R31/31716
摘要： A test system and method for testing a serializer/de-serializer system. The system includes a pair of serializer/de-serializers each having a serial data receive port and a serial data transmit port. The serializer/de-serializers are adapted to be placed in a loop-back mode in response to a loop-back signal to pass data fed to the serial data receive port to the serial data transmit port. A backplane connects the serial data transmit port of one serializer/de-serializer to the serial data receive port of a second one of the serializer/de-serializers. A tester passes data to the first serial data receive port and receives data from the data transmit port of the second one of the serializer/de-serializers with both serializer/de-serializes placed in the loop-back mode.
摘要翻译：用于测试串行器/解串器系统的测试系统和方法。该系统包括一对串行器/解串器，每个具有串行数据接收端口和串行数据传输端口。串行器/解串器适合于回送模式，以响应回送信号将馈送到串行数据接收端口的数据传送到串行数据传输端口。背板将串行器/解串器的串行数据发送端口连接到串行器/解串器的第二个串行数据接收端口。测试仪将数据传送到第一个串行数据接收端口，并从串行器/解串行器的第二个串行器/解串行器的数据发送端口接收数据，并将串行器/解串行器放置在循环模式中。

3. 发明授权

US06973593B1 System analyzer for a data storage system 有权
标题翻译：用于数据存储系统的系统分析仪
公开(公告)号：US06973593B1
公开(公告)日：2005-12-06
申请号：US10100458
申请日：2002-03-18
申请人： Mark Zani , Ofer Porat , Alexander Rabinovich
发明人： Mark Zani , Ofer Porat , Alexander Rabinovich
IPC分类号： G06F11/00 , G06F11/263
CPC分类号： G06F11/263
摘要： A system analyzer for a data storage system has a control module and a memory module. The system analyzer includes a logic analyzer, an input port that couples to the data storage system, an output port that couples to the logic analyzer, and a pre-processor which is interconnected between the input port and the output port. The pre-processor is configured to receive, while a first point-to-point signal is exchanged between the control module and the memory module, a second point-to-point signal which is a copy of the first point-to-point signal. The pre-processor is further configured to generate a pre-processed signal based on the second point-to-point signal, and to provide the pre-processed signal to the logic analyzer.
摘要翻译：用于数据存储系统的系统分析器具有控制模块和存储器模块。系统分析器包括逻辑分析器，耦合到数据存储系统的输入端口，耦合到逻辑分析器的输出端口以及在输入端口和输出端口之间互连的预处理器。预处理器被配置为在控制模块和存储器模块之间交换第一点对点信号时接收作为第一点对点信号的副本的第二点对点信号。预处理器还被配置为基于第二点对点信号产生预处理的信号，并且将预处理的信号提供给逻辑分析器。

4. 发明授权

US07752340B1 Atomic command retry in a data storage system 有权
标题翻译：原子命令在数据存储系统中重试
公开(公告)号：US07752340B1
公开(公告)日：2010-07-06
申请号：US11395621
申请日：2006-03-31
申请人： Ofer Porat , Armen Avakian , Michael Daigle , Paul Scharlach
发明人： Ofer Porat , Armen Avakian , Michael Daigle , Paul Scharlach
IPC分类号： G06F3/00
CPC分类号： G06F11/1443
摘要： A data transfer retry method includes: A. receiving a particular atomic data transfer command from a director; B. processing identification information associated with the particular atomic data transfer command; C. comparing the identification information associated with the particular atomic data transfer command to identification information of a previous atomic data transfer command received from the director; D. determining that the particular atomic data transfer command is a retry command of the previous atomic data transfer command received from the director; E. determining a status of the execution of the previous atomic data transfer command received from the director; and F. processing the particular atomic data transfer command based on the status of the execution of the previous atomic data transfer command determined in Step E.
摘要翻译：数据传输重试方法包括：A.从导演接收特定的原子数据传输命令; B.与特定原子数据传输命令相关联的处理识别信息; C.将与特定原子数据传输命令相关联的识别信息与从导演器接收的先前原子数据传送命令的识别信息进行比较; D.确定特定原子数据传输命令是从导演器接收的先前原子数据传送命令的重试命令; E.确定从导演接收的先前的原子数据传送命令的执行状态; 和F.基于在步骤E中确定的先前的原子数据传送命令的执行状态来处理特定的原子数据传送命令。

5. 发明授权

US07574555B2 Memory system having daisy chained memory controllers 有权
标题翻译：具有菊花链式存储控制器的存储系统
公开(公告)号：US07574555B2
公开(公告)日：2009-08-11
申请号：US11083571
申请日：2005-03-18
申请人： Ofer Porat , Brian K. Campbell , Brian D. Magnuson , Stephen Scaringella
发明人： Ofer Porat , Brian K. Campbell , Brian D. Magnuson , Stephen Scaringella
IPC分类号： G06F12/00 , G06F12/02 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0866 , G06F12/0893 , G06F13/1684 , G06F2212/263
摘要： A memory system having a plurality of sets of memory modules. The system includes a plurality of sets of memory controllers, each one of the memory controllers being coupled to a corresponding one of the plurality of sets of memory modules. The system includes a port for providing address and read/write control signals to the memory system. The memory controllers are interconnected in a daisy chain arrangement to the port.
摘要翻译：一种具有多组存储器模块的存储器系统。该系统包括多组存储器控制器，每个存储器控制器耦合到多组存储器模块中的对应的一组存储器模块。该系统包括用于向存储器系统提供地址和读/写控制信号的端口。存储器控制器以菊花链方式互连到端口。

6. 发明申请

US20060212622A1 Memory system 有权
标题翻译：内存系统
公开(公告)号：US20060212622A1
公开(公告)日：2006-09-21
申请号：US11083571
申请日：2005-03-18
申请人： Ofer Porat , Brian Campbell , Brian Magnuson , Stephen Scaringella
发明人： Ofer Porat , Brian Campbell , Brian Magnuson , Stephen Scaringella
IPC分类号： G06F13/38
CPC分类号： G06F12/0866 , G06F12/0893 , G06F13/1684 , G06F2212/263
摘要： A memory system having a plurality of sets of memory modules. The system includes a plurality of sets of memory controllers, each one of the memory controllers being coupled to a corresponding one of the plurality of sets of memory modules. The system includes a port for providing address and read/write control signals to the memory system. The memory controllers are interconnected in a daisy chain arrangement to the port.
摘要翻译：一种具有多组存储器模块的存储器系统。该系统包括多组存储器控制器，每个存储器控制器耦合到多组存储器模块中的对应的一组存储器模块。该系统包括用于向存储器系统提供地址和读/写控制信号的端口。存储器控制器以菊花链方式互连到端口。

7. 发明授权

US07275201B1 Memory system 有权
标题翻译：内存系统
公开(公告)号：US07275201B1
公开(公告)日：2007-09-25
申请号：US11104735
申请日：2005-04-13
申请人： Ofer Porat , James Tryhubczak , Brian K. Campbell , Clayton A. Curry
发明人： Ofer Porat , James Tryhubczak , Brian K. Campbell , Clayton A. Curry
IPC分类号： H03M13/00
CPC分类号： H03M13/17 , G06F11/1044 , H03M13/09 , H03M13/13 , H03M13/373
摘要： A system having memory modules for storing nibbles of a word. The nibbles include an error correction/detection code. A memory controller is response to clock pulses to produce a read command. A synchronizer is responsive to the read nibbles and an associated read strobe signal for synchronizing the read nibbles and the read strobes to the clock pulses. A detection section is responsive to the clock pulses and the read command for producing a time window representative of a time duration during which each of the read strobes is expected. The detection system is responsive to each one of the read strobes and the produced time window for producing, for each one of the read strobes, a corresponding one of a plurality of NIBBLE ERROR signals. Each one of the NIBBLE ERROR signals indicates whether the corresponding one of the read strobes is within the produced window or is absent from such window.
摘要翻译：一种具有用于存储单词的半字节的存储器模块的系统。该半字节包括纠错/检测码。存储器控制器响应时钟脉冲以产生读取命令。同步器响应于读半字节和相关联的读选通信号，用于将读半字节和读选通脉冲同步到时钟脉冲。检测部分响应于时钟脉冲和读取命令，用于产生表示每个读取选通脉冲期间的持续时间的时间窗口。检测系统响应读选通和产生的时间窗中的每一个，为每个读选通产生多个NIBBLE ERROR信号中相应的一个。 NIBBLE ERROR信号中的每一个指示读取选通中的相应一个是否在生成的窗口内，或者不存在于该窗口中。

8. 发明授权

US07272668B1 System having backplane performance capability selection logic 有权
标题翻译：具有背板性能能力选择逻辑的系统
公开(公告)号：US07272668B1
公开(公告)日：2007-09-18
申请号：US10606872
申请日：2003-06-26
申请人： John K. Walton , Ofer Porat , Christopher S. MacLellan , Daniel Castel , Kendell A. Chilton , Brian K. Campbell , Gregory S. Robidoux , Brian D. Magnuson
发明人： John K. Walton , Ofer Porat , Christopher S. MacLellan , Daniel Castel , Kendell A. Chilton , Brian K. Campbell , Gregory S. Robidoux , Brian D. Magnuson
IPC分类号： G06F3/00 , G06F13/00 , G06F13/42 , G06F11/00
CPC分类号： G06F1/181 , G06F1/184 , G06F1/185 , G06F1/186 , G06F3/0601 , G06F2003/0692
摘要： A system having a plurality of printed circuit broads each one having an electrical component thereon. A backplane carries a signal indicative of a performance characteristic of the electrical components on the plurality of printed circuit boards plugged into such backplane. The performance characteristic may be, for example component speed, operating protocol, etc. System start-up is interrupted upon detection of such incompatibility. After start up, upon plugging an additional printed circuit broad having an electrical component thereon with an operating incompatible with the electrical components on the plurality of printed circuit boards into the backplane, the electrical component on such additional printed circuit will not be electrically coupled to the electrical component on the additional printed circuit board from the electrical components of the plurality of printed circuit boards.
摘要翻译：具有多个印刷电路的系统具有在其上具有电气部件的每个印刷电路。背板携带指示插入到该背板中的多个印刷电路板上的电气部件的性能特征的信号。性能特征可以是例如组件速度，操作协议等。在检测到这种不兼容性时，系统启动被中断。在启动之后，当插入其上具有电气部件的附加印刷电路，其操作与多个印刷电路板上的电气部件不兼容的操作进入背板时，这种附加印刷电路上的电气部件将不会电耦合到电子部件在多个印刷电路板的电气部件上的附加印刷电路板上。

9. 发明申请

US20080127576A1 Hiddn Roof Gutter System 审中-公开
标题翻译： Hiddn屋顶沟槽系统
公开(公告)号：US20080127576A1
公开(公告)日：2008-06-05
申请号：US11566219
申请日：2006-12-03
申请人： Ofer Porat
发明人： Ofer Porat
IPC分类号： E04D13/08
CPC分类号： E04D13/064 , E04D1/30 , E04D13/0641 , E04D13/0643 , E04D13/0645
摘要： In its simplest from, the hidden rain gutter of the present invention consists of a trough having a closed cross-sectional contour that is enclosed for the most of its periphery, having an opening in its upper section adjacent to the drain opening in the roof surface layer through which rainwater is introduced into the trough. The hidden rain gutter of the present invention is configured with at least one drainage outlet and at least one distal end spaced apart from the drainage outlet. The hidden rain gutter element defines a drainage vector between the distal end and the drainage outlet In one preferred deployment of the hidden rain gutter of the present invention the drainage vector is parallel to the plane of the roof surface layer with the distal end deployed higher on the slope of the roof than the drainage outlet such that rainwater falling into the rain gutter element is directed toward the drainage outlet. In a most preferred deployment, the roofing system includes a roofing underlay deployed on the roof structural frame with the roof surface layer supported above the roofing underlay by battens and counter-battens. The planes of the roofing underlay and the roof surface layer are, therefore, substantially parallel and spaced apart at a distance of approximately 6-12 centimeters therebetween. The hidden rain gutter of the present invention is configured for deployment in that space provided between the roofing underlay and the roof surface layer.
摘要翻译：在本发明的最简单的方案中，隐藏的雨水沟由具有封闭的横截面轮廓的槽构成，该轮廓围绕其大部分周边被封闭，在其上部中具有与屋顶表面中的排水开口相邻的开口将雨水引入槽中的层。本发明的隐藏式雨水槽配置有至少一个排水口和与排水口间隔开的至少一个远端。隐藏的雨水槽元件限定了远端和排水口之间的排水矢量。在本发明的隐藏雨沟的一个优选布置中，排水矢量平行于屋顶表面层的平面，远端展开较高屋顶的倾斜比排水口，使得雨水落入雨水槽元件中的雨水指向排水口。在最优选的部署中，屋顶系统包括部分在屋顶结构框架上的屋顶底板，屋顶表面层通过板条和反对板支撑在屋顶底层上方。因此，屋面垫层和屋顶表面层的平面基本上平行并间隔开，间距约为6-12厘米。本发明的隐蔽雨沟构造成用于展开在设置在屋顶底层和屋顶表面层之间的空间中。

10. 发明授权

US07143306B2 Data storage system 有权
标题翻译：数据存储系统
公开(公告)号：US07143306B2
公开(公告)日：2006-11-28
申请号：US10403262
申请日：2003-03-31
申请人： Ofer Porat , Brian K. Campbell , Jane Xu , Eric J. Bruno , Paul C. Wilson
发明人： Ofer Porat , Brian K. Campbell , Jane Xu , Eric J. Bruno , Paul C. Wilson
IPC分类号： G06F11/00
CPC分类号： G06F12/084 , G06F11/2053 , G06F12/0868 , G06F2212/261
摘要： A system interface having a cache memory and a plurality of directors. Each one of the plurality of directors includes a data pipe coupled between an input of such one of the directors. The data pipe includes a data pipe memory and a data pipe memory controller for controlling the data pipe memory. Each one of the directors includes microprocessor coupled to the data pipe memory controller. The system includes a switching network coupled to the cache memory to transfer data between the memory and: (a) the input of a selected one of the plurality of directors through the data pipe memory; (b) the microprocessor and the data pipe memory through the data pipe memory controller of a selected one of the plurality of directors; and (c) the microprocessor and the data pipe memory controller while by-passing the data pipe memory of a selected one of the plurality of directors.
摘要翻译：一种具有高速缓冲存储器和多个导向器的系统接口。多个董事中的每一个都包括耦合在这样一个董事的输入之间的数据管。数据管道包括数据管道存储器和用于控制数据管道存储器的数据管道存储器控制器。每个导体包括耦合到数据管存储器控制器的微处理器。该系统包括耦合到高速缓存存储器以在存储器之间传送数据的切换网络：（a）通过数据管道存储器输入多个导向器中的所选择的一个; （b）所述微处理器和所述数据管道存储器，通过所述多个董事中选定的一个的所述数据管道存储器控制器; 以及（c）所述微处理器和所述数据管存储器控制器，同时绕过所述多个导向器中所选择的一个的所述数据管道存储器。

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