专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07272668B1 System having backplane performance capability selection logic 有权
标题翻译：具有背板性能能力选择逻辑的系统
公开(公告)号：US07272668B1
公开(公告)日：2007-09-18
申请号：US10606872
申请日：2003-06-26
申请人： John K. Walton , Ofer Porat , Christopher S. MacLellan , Daniel Castel , Kendell A. Chilton , Brian K. Campbell , Gregory S. Robidoux , Brian D. Magnuson
发明人： John K. Walton , Ofer Porat , Christopher S. MacLellan , Daniel Castel , Kendell A. Chilton , Brian K. Campbell , Gregory S. Robidoux , Brian D. Magnuson
IPC分类号： G06F3/00 , G06F13/00 , G06F13/42 , G06F11/00
CPC分类号： G06F1/181 , G06F1/184 , G06F1/185 , G06F1/186 , G06F3/0601 , G06F2003/0692
摘要： A system having a plurality of printed circuit broads each one having an electrical component thereon. A backplane carries a signal indicative of a performance characteristic of the electrical components on the plurality of printed circuit boards plugged into such backplane. The performance characteristic may be, for example component speed, operating protocol, etc. System start-up is interrupted upon detection of such incompatibility. After start up, upon plugging an additional printed circuit broad having an electrical component thereon with an operating incompatible with the electrical components on the plurality of printed circuit boards into the backplane, the electrical component on such additional printed circuit will not be electrically coupled to the electrical component on the additional printed circuit board from the electrical components of the plurality of printed circuit boards.
摘要翻译：具有多个印刷电路的系统具有在其上具有电气部件的每个印刷电路。背板携带指示插入到该背板中的多个印刷电路板上的电气部件的性能特征的信号。性能特征可以是例如组件速度，操作协议等。在检测到这种不兼容性时，系统启动被中断。在启动之后，当插入其上具有电气部件的附加印刷电路，其操作与多个印刷电路板上的电气部件不兼容的操作进入背板时，这种附加印刷电路上的电气部件将不会电耦合到电子部件在多个印刷电路板的电气部件上的附加印刷电路板上。

2. 发明授权

US06910145B2 Data transmission across asynchronous clock domains 有权
标题翻译：跨异步时钟域的数据传输
公开(公告)号：US06910145B2
公开(公告)日：2005-06-21
申请号：US10021949
申请日：2001-12-13
申请人： Christopher S. MacLellan , Gregory S. Robidoux , John K. Walton , Kendell A. Chilton
发明人： Christopher S. MacLellan , Gregory S. Robidoux , John K. Walton , Kendell A. Chilton
IPC分类号： G06F3/06 , G06F12/00 , G06F13/00 , H04L7/02
CPC分类号： G06F3/061 , G06F3/0656 , G06F3/067 , H04L7/005 , H04L7/02
摘要： In one embodiment of the present invention, a system is provided for use in transmitting data and related control information from a first clock domain to a second clock domain. The system may include a first logic section that may generate respective identification information that may be used to identify respective types of information represented by respective data and related control information. The system may also include memory that may receive and store, at a first clock rate used in the first clock domain, the respective data and related control information. The memory also may store, in association with the respective data and related control information, the respective identification information. The memory may be configured to permit the retrieval, at a second clock rate used in the second clock domain, of the respective data, the respective related control information, and the respective identification information stored in the memory.
摘要翻译：在本发明的一个实施例中，提供了一种用于将数据和相关控制信息从第一时钟域传送到第二时钟域的系统。该系统可以包括第一逻辑部分，该第一逻辑部分可以生成相应的识别信息，所述识别信息可用于识别由相应数据和相关控制信息表示的相应信息类型。系统还可以包括可以以第一时钟域中使用的第一时钟速率接收和存储相应数据和相关控制信息的存储器。存储器还可以与各个数据和相关控制信息相关联地存储相应的标识信息。存储器可以被配置为允许在第二时钟域中使用的第二时钟速率检索相应数据，相应的相关控制信息以及存储在存储器中的相应标识信息。

3. 发明授权

US07107424B1 Memory read strobe pulse optimization training system 有权
标题翻译：存储器读选通脉冲优化训练系统
公开(公告)号：US07107424B1
公开(公告)日：2006-09-12
申请号：US10809733
申请日：2004-03-25
申请人： Armen D. Avakian , Adam C. Peltz , Krzysztof Dobecki , Gregory S. Robidoux
发明人： Armen D. Avakian , Adam C. Peltz , Krzysztof Dobecki , Gregory S. Robidoux
IPC分类号： G06F13/00 , G06F13/43 , G11C7/00 , G06F1/04 , G06F1/06 , G06F1/08
CPC分类号： G06F13/4243
摘要： A method for determining a read strobe pulse delay for data read from a memory having a plurality of memory chips. Each one of the chips provides data along with an associated read strobe pulse. The data read from each one of the plurality of chips is stored in a corresponding one of a plurality of storage devices in response to the read strobe pulse associated with such one of the plurality of chips. A training system determines a delay which when applied in to the plurality of read strobe pulses enables valid read data from the plurality of memory chips to be stored in each one of the plurality of the storage device in response to the read strobe pulses being delayed by the read pulse strobe delay. A process is used to enable preservation of the user data during the training process for use subsequent to the training process.
摘要翻译：一种用于确定从具有多个存储器芯片的存储器读取的数据的读选通脉冲延迟的方法。每个芯片都提供数据以及相关的读选通脉冲。响应于与多个芯片中的一个芯片相关联的读选通脉冲，从多个芯片中的每一个读取的数据被存储在多个存储设备中的对应的一个中。训练系统确定延迟，当应用于多个读取选通脉冲时，响应于读取的选通脉冲被延迟，多个存储器芯片中的有效读取数据被存储在多个存储器件的每一个中读脉冲选通延时。一个过程用于在训练过程中保持用户数据，以便在训练过程之后使用。

4. 发明授权

US07016240B1 Non-destructive memory read strobe pulse optimization training system 有权
标题翻译：非破坏性存储器读选通脉冲优化训练系统
公开(公告)号：US07016240B1
公开(公告)日：2006-03-21
申请号：US10809732
申请日：2004-03-25
申请人： Armen D. Avakian , Adam C. Peltz , Gregory S. Robidoux
发明人： Armen D. Avakian , Adam C. Peltz , Gregory S. Robidoux
IPC分类号： G11C7/00
CPC分类号： G06F13/1689
摘要： A method for determining a read strobe pulse delay for data read from a memory having a plurality of memory chips. Each one of the chips provides data along with an associated read strobe pulse. The data read from each one of the plurality of chips is stored in a corresponding one of a plurality of storage devices in response to the read strobe pulse associated with such one of the plurality of chips. A training system determines a delay which when applied in to the plurality of read strobe pulses enables valid read data from the plurality of memory chips to be stored in each one of the plurality of the storage device in response to the read strobe pulses being delayed by the read pulse strobe delay. A process is used to enable preservation of the user data during the training process for use subsequent to the training process.
摘要翻译：一种用于确定从具有多个存储器芯片的存储器读取的数据的读选通脉冲延迟的方法。每个芯片都提供数据以及相关的读选通脉冲。响应于与多个芯片中的一个芯片相关联的读选通脉冲，从多个芯片中的每一个读取的数据被存储在多个存储设备中的对应的一个中。训练系统确定延迟，当应用于多个读取选通脉冲时，响应于读取的选通脉冲被延迟，多个存储器芯片中的有效读取数据被存储在多个存储器件的每一个中读脉冲选通延时。一个过程用于在训练过程中保持用户数据，以便在训练过程之后使用。

5. 发明授权

US08959173B1 Non-disruptive load-balancing of virtual machines between data centers 有权
标题翻译：数据中心之间虚拟机的无中断负载平衡
公开(公告)号：US08959173B1
公开(公告)日：2015-02-17
申请号：US12895174
申请日：2010-09-30
申请人： Gregory S. Robidoux , Balakrishnan Ganeshan , Yaron Dar , Kenneth J. Taylor , Txomin Barturen , Bradford B. Glade
发明人： Gregory S. Robidoux , Balakrishnan Ganeshan , Yaron Dar , Kenneth J. Taylor , Txomin Barturen , Bradford B. Glade
IPC分类号： G06F15/16 , G06F15/167 , G06F15/177 , G06F15/173
CPC分类号： G06F9/5088 , G06F3/0619 , G06F3/065 , G06F3/0665 , G06F3/0689 , G06F9/4868 , G06F2209/5019
摘要： A method, system and program product for enabling migration of Virtual Machines with concurrent access to data across two geographically disperse sites to enable load balancing across the two geographically disperse sites, by presenting over a network a read writable logical volume at a first site, presenting over a network a read writable logical volume at a second geographically disparate site; wherein the first volume and the second volume are configured to contain the same information, and enabling read write access to the volume at the first site or the volume at the second site for a first virtual machine while keeping the data consistent between the two sites to enable transparent migration of the virtual machine to load balancing across the two sites according to at least one load balancing metric.
摘要翻译：一种方法，系统和程序产品，用于通过在两个地理上分散的站点之间并行访问数据来实现虚拟机的迁移，以通过在网络上呈现第一站点上的可读写逻辑卷来呈现跨两个地理分散站点的负载平衡，呈现通过网络在第二地理上不同的站点上的可读写逻辑卷; 其中所述第一卷和所述第二卷被配置为包含相同的信息，并且对于第一虚拟机启用对所述第一站点处的卷的读取写入访问或第二站点处的卷的读写访问，同时保持所述两个站点之间的数据一致启用虚拟机的透明迁移，以便根据至少一个负载均衡度量来跨两个站点进行负载平衡。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式