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1. 发明授权

US07143306B2 Data storage system 有权
标题翻译：数据存储系统
公开(公告)号：US07143306B2
公开(公告)日：2006-11-28
申请号：US10403262
申请日：2003-03-31
申请人： Ofer Porat , Brian K. Campbell , Jane Xu , Eric J. Bruno , Paul C. Wilson
发明人： Ofer Porat , Brian K. Campbell , Jane Xu , Eric J. Bruno , Paul C. Wilson
IPC分类号： G06F11/00
CPC分类号： G06F12/084 , G06F11/2053 , G06F12/0868 , G06F2212/261
摘要： A system interface having a cache memory and a plurality of directors. Each one of the plurality of directors includes a data pipe coupled between an input of such one of the directors. The data pipe includes a data pipe memory and a data pipe memory controller for controlling the data pipe memory. Each one of the directors includes microprocessor coupled to the data pipe memory controller. The system includes a switching network coupled to the cache memory to transfer data between the memory and: (a) the input of a selected one of the plurality of directors through the data pipe memory; (b) the microprocessor and the data pipe memory through the data pipe memory controller of a selected one of the plurality of directors; and (c) the microprocessor and the data pipe memory controller while by-passing the data pipe memory of a selected one of the plurality of directors.
摘要翻译：一种具有高速缓冲存储器和多个导向器的系统接口。多个董事中的每一个都包括耦合在这样一个董事的输入之间的数据管。数据管道包括数据管道存储器和用于控制数据管道存储器的数据管道存储器控制器。每个导体包括耦合到数据管存储器控制器的微处理器。该系统包括耦合到高速缓存存储器以在存储器之间传送数据的切换网络：（a）通过数据管道存储器输入多个导向器中的所选择的一个; （b）所述微处理器和所述数据管道存储器，通过所述多个董事中选定的一个的所述数据管道存储器控制器; 以及（c）所述微处理器和所述数据管存储器控制器，同时绕过所述多个导向器中所选择的一个的所述数据管道存储器。

2. 发明授权

US06981111B1 Data storage system 有权
标题翻译：数据存储系统
公开(公告)号：US06981111B1
公开(公告)日：2005-12-27
申请号：US10403263
申请日：2003-03-31
申请人： Ofer Porat , Brian K. Campbell , Jane Xu , Eric J. Bruno
发明人： Ofer Porat , Brian K. Campbell , Jane Xu , Eric J. Bruno
IPC分类号： G06F12/00 , G06F13/40
CPC分类号： G06F13/4027
摘要： A system and method are provided for transferring data appended with a tag indicating whether the transmit data is data allowed to be re-transmitted or inhibited from being re-transmitted to a memory section. A buffer is fed with the transmit data from a data source for transmit data to the memory section. A receiver is receives data from the memory section and checks such received data for errors. Either the transmit data from the data source is coupled to the memory section in absence of a detected error or the data in the buffer is coupled to the memory section when an error has been detected and the data has been tagged with an indication that the transmit data is data allowed to be re-transmitted; selectively.
摘要翻译：提供了一种系统和方法，用于传送附加有指示发送数据是否被允许被重传或禁止的数据被重新发送到存储器部分的标签的数据。向数据源馈送缓冲器，用于发送数据到存储器部分。接收机从存储器部分接收数据并检查这样的接收到的数据是否存在错误。在没有检测到的错误的情况下，来自数据源的发送数据被耦合到存储器部分，或者当已经检测到错误并且已经利用指示发送的指示将缓冲器中的数据耦合到存储器部分时数据是允许重传的数据; 选择性地。

3. 发明授权

US07574555B2 Memory system having daisy chained memory controllers 有权
标题翻译：具有菊花链式存储控制器的存储系统
公开(公告)号：US07574555B2
公开(公告)日：2009-08-11
申请号：US11083571
申请日：2005-03-18
申请人： Ofer Porat , Brian K. Campbell , Brian D. Magnuson , Stephen Scaringella
发明人： Ofer Porat , Brian K. Campbell , Brian D. Magnuson , Stephen Scaringella
IPC分类号： G06F12/00 , G06F12/02 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0866 , G06F12/0893 , G06F13/1684 , G06F2212/263
摘要： A memory system having a plurality of sets of memory modules. The system includes a plurality of sets of memory controllers, each one of the memory controllers being coupled to a corresponding one of the plurality of sets of memory modules. The system includes a port for providing address and read/write control signals to the memory system. The memory controllers are interconnected in a daisy chain arrangement to the port.
摘要翻译：一种具有多组存储器模块的存储器系统。该系统包括多组存储器控制器，每个存储器控制器耦合到多组存储器模块中的对应的一组存储器模块。该系统包括用于向存储器系统提供地址和读/写控制信号的端口。存储器控制器以菊花链方式互连到端口。

4. 发明授权

US07275201B1 Memory system 有权
标题翻译：内存系统
公开(公告)号：US07275201B1
公开(公告)日：2007-09-25
申请号：US11104735
申请日：2005-04-13
申请人： Ofer Porat , James Tryhubczak , Brian K. Campbell , Clayton A. Curry
发明人： Ofer Porat , James Tryhubczak , Brian K. Campbell , Clayton A. Curry
IPC分类号： H03M13/00
CPC分类号： H03M13/17 , G06F11/1044 , H03M13/09 , H03M13/13 , H03M13/373
摘要： A system having memory modules for storing nibbles of a word. The nibbles include an error correction/detection code. A memory controller is response to clock pulses to produce a read command. A synchronizer is responsive to the read nibbles and an associated read strobe signal for synchronizing the read nibbles and the read strobes to the clock pulses. A detection section is responsive to the clock pulses and the read command for producing a time window representative of a time duration during which each of the read strobes is expected. The detection system is responsive to each one of the read strobes and the produced time window for producing, for each one of the read strobes, a corresponding one of a plurality of NIBBLE ERROR signals. Each one of the NIBBLE ERROR signals indicates whether the corresponding one of the read strobes is within the produced window or is absent from such window.
摘要翻译：一种具有用于存储单词的半字节的存储器模块的系统。该半字节包括纠错/检测码。存储器控制器响应时钟脉冲以产生读取命令。同步器响应于读半字节和相关联的读选通信号，用于将读半字节和读选通脉冲同步到时钟脉冲。检测部分响应于时钟脉冲和读取命令，用于产生表示每个读取选通脉冲期间的持续时间的时间窗口。检测系统响应读选通和产生的时间窗中的每一个，为每个读选通产生多个NIBBLE ERROR信号中相应的一个。 NIBBLE ERROR信号中的每一个指示读取选通中的相应一个是否在生成的窗口内，或者不存在于该窗口中。

5. 发明授权

US07272668B1 System having backplane performance capability selection logic 有权
标题翻译：具有背板性能能力选择逻辑的系统
公开(公告)号：US07272668B1
公开(公告)日：2007-09-18
申请号：US10606872
申请日：2003-06-26
申请人： John K. Walton , Ofer Porat , Christopher S. MacLellan , Daniel Castel , Kendell A. Chilton , Brian K. Campbell , Gregory S. Robidoux , Brian D. Magnuson
发明人： John K. Walton , Ofer Porat , Christopher S. MacLellan , Daniel Castel , Kendell A. Chilton , Brian K. Campbell , Gregory S. Robidoux , Brian D. Magnuson
IPC分类号： G06F3/00 , G06F13/00 , G06F13/42 , G06F11/00
CPC分类号： G06F1/181 , G06F1/184 , G06F1/185 , G06F1/186 , G06F3/0601 , G06F2003/0692
摘要： A system having a plurality of printed circuit broads each one having an electrical component thereon. A backplane carries a signal indicative of a performance characteristic of the electrical components on the plurality of printed circuit boards plugged into such backplane. The performance characteristic may be, for example component speed, operating protocol, etc. System start-up is interrupted upon detection of such incompatibility. After start up, upon plugging an additional printed circuit broad having an electrical component thereon with an operating incompatible with the electrical components on the plurality of printed circuit boards into the backplane, the electrical component on such additional printed circuit will not be electrically coupled to the electrical component on the additional printed circuit board from the electrical components of the plurality of printed circuit boards.
摘要翻译：具有多个印刷电路的系统具有在其上具有电气部件的每个印刷电路。背板携带指示插入到该背板中的多个印刷电路板上的电气部件的性能特征的信号。性能特征可以是例如组件速度，操作协议等。在检测到这种不兼容性时，系统启动被中断。在启动之后，当插入其上具有电气部件的附加印刷电路，其操作与多个印刷电路板上的电气部件不兼容的操作进入背板时，这种附加印刷电路上的电气部件将不会电耦合到电子部件在多个印刷电路板的电气部件上的附加印刷电路板上。

6. 发明授权

US07712004B1 Method of and system for error checking in a data storage system 有权
标题翻译：数据存储系统中错误检查的方法和系统
公开(公告)号：US07712004B1
公开(公告)日：2010-05-04
申请号：US10675002
申请日：2003-09-30
申请人： Brian K. Campbell , Kendell A. Chilton , Christopher S. MacLellan , Ofer Porat
发明人： Brian K. Campbell , Kendell A. Chilton , Christopher S. MacLellan , Ofer Porat
IPC分类号： H04L1/00
CPC分类号： H04L1/0082 , H04L1/0061
摘要： An error checking system includes an input device for receiving a data element including parity information; a parity check device for checking the parity information of the data element to determine whether the data element is valid; a CRC generator coupled to the parity check device for generating a CRC for the data element; and an output device for transmitting the data element with the parity information and CRC to a downstream device over a transmission link. The parity check device is operative to output a corruption signal to the CRC generator if the parity check device determines that the data element is invalid, to instruct the CRC generator to corrupt the CRC generation for that data element.
摘要翻译：错误检查系统包括用于接收包括奇偶校验信息的数据元素的输入装置; 奇偶校验装置，用于检查数据元素的奇偶校验信息，以确定数据元素是否有效; 耦合到所述奇偶校验装置的CRC发生器，用于生成所述数据元素的CRC; 以及用于通过传输链路将具有奇偶校验信息和CRC的数据元素发送到下游设备的输出设备。如果奇偶校验设备确定数据元素无效，则奇偶校验设备可操作以将错误信号输出到CRC发生器，以指示CRC发生器破坏该数据元素的CRC生成。

7. 发明申请

US20120233693A1 METHODS AND SYSTEMS FOR FULL PATTERN MATCHING IN HARDWARE 有权
标题翻译：硬件完全匹配的方法与系统
公开(公告)号：US20120233693A1
公开(公告)日：2012-09-13
申请号：US13043287
申请日：2011-03-08
申请人： Ronald S. Stites , Craig D. Botkin , Brian K. Campbell
发明人： Ronald S. Stites , Craig D. Botkin , Brian K. Campbell
IPC分类号： G06F11/00
CPC分类号： H04L63/1416 , G06F2207/025
摘要： Methods and systems are provided for hardware-based pattern matching. In an embodiment, an intrusion-prevention system (IPS) identifies a full match between a subject data word comprising subject-data blocks and a signature data pattern comprising signature-data blocks. The IPS receives the subject data word via a network interface, and thereafter makes a partial-match determination that two or more but less than all of the subject-data blocks respectively match the same number of the signature-data blocks stored in partial-match hardware with respect to both value and position. Thereafter, the IPS makes a full-match determination that all of the subject-data blocks respectively match all of the signature-data blocks stored in the IPS's full-match hardware with respect to both value and position. The IPS then stores an indicator that the full-match determination has been made, and may carry out one or more additional intrusion-prevention responses as well.
摘要翻译：提供了基于硬件的模式匹配的方法和系统。在一个实施例中，入侵防御系统（IPS）识别包括主体数据块的主题数据字和包括签名数据块的签名数据模式之间的完全匹配。 IPS通过网络接口接收对象数据字，然后进行部分匹配确定，其中两个或更多个但少于所有主题数据块分别与存储在部分匹配中的相同数量的签名数据块匹配硬件相对于价值和位置。此后，IPS进行完全匹配确定，即所有主题数据块分别与存储在IPS的全匹配硬件中的所有签名数据块相对于值和位置相匹配。然后，IPS存储已经进行完全匹配确定的指示符，并且还可以执行一个或多个另外的入侵防止响应。

8. 发明授权

US08458796B2 Methods and systems for full pattern matching in hardware 有权
标题翻译：硬件全模式匹配的方法和系统
公开(公告)号：US08458796B2
公开(公告)日：2013-06-04
申请号：US13043287
申请日：2011-03-08
申请人： Ronald S. Stites , Craig D. Botkin , Brian K. Campbell
发明人： Ronald S. Stites , Craig D. Botkin , Brian K. Campbell
IPC分类号： G06F11/00 , G06F17/00 , G06F11/30
CPC分类号： H04L63/1416 , G06F2207/025
摘要： Methods and systems are provided for hardware-based pattern matching. In an embodiment, an intrusion-prevention system (IPS) identifies a full match between a subject data word comprising subject-data blocks and a signature data pattern comprising signature-data blocks. The IPS receives the subject data word via a network interface, and thereafter makes a partial-match determination that two or more but less than all of the subject-data blocks respectively match the same number of the signature-data blocks stored in partial-match hardware with respect to both value and position. Thereafter, the IPS makes a full-match determination that all of the subject-data blocks respectively match all of the signature-data blocks stored in the IPS's full-match hardware with respect to both value and position. The IPS then stores an indicator that the full-match determination has been made, and may carry out one or more additional intrusion-prevention responses as well.
摘要翻译：提供了基于硬件的模式匹配的方法和系统。在一个实施例中，入侵防御系统（IPS）识别包括主体数据块的主题数据字和包括签名数据块的签名数据模式之间的完全匹配。 IPS通过网络接口接收对象数据字，然后进行部分匹配确定，其中两个或多个但少于所有对象数据块分别与存储在部分匹配中的相同数量的签名数据块匹配硬件相对于价值和位置。此后，IPS进行完全匹配确定，即所有主题数据块分别与存储在IPS的全匹配硬件中的所有签名数据块相对于值和位置相匹配。然后，IPS存储已经进行完全匹配确定的指示符，并且还可以执行一个或多个另外的入侵防止响应。

9. 发明申请

US20140090057A1 METHODS AND SYSTEMS FOR FULL PATTERN MATCHING IN HARDWARE 审中-公开
标题翻译：硬件完全匹配的方法与系统
公开(公告)号：US20140090057A1
公开(公告)日：2014-03-27
申请号：US14003020
申请日：2012-03-01
申请人： Ronald S. Stites , Craig D. Botkin , Brian K. Campbell
发明人： Ronald S. Stites , Craig D. Botkin , Brian K. Campbell
IPC分类号： H04L29/06
CPC分类号： H04L63/1416 , G06F2207/025
摘要： Methods and systems are provided for hardware-based pattern matching. In an embodiment, an intrusion-prevention system (IPS) identifies a full match between a subject data word comprising subject-data blocks and a signature data pattern comprising signature-data blocks. The IPS receives the subject data word via a network interface, and thereafter makes a partial-match determination that two or more but less than all of the subject-data blocks respectively match the same number of the signature-data blocks stored in partial-match hardware with respect to both value and position. Thereafter, the IPS makes a full-match determination that all of the subject-data blocks respectively match all of the signature-data blocks stored in the IPS's full-match hardware with respect to both value and position. The IPS then stores an indicator that the full-match determination has been made, and may carry out one or more additional intrusion-prevention responses as well.
摘要翻译：提供了基于硬件的模式匹配的方法和系统。在一个实施例中，入侵防御系统（IPS）识别包括主体数据块的主题数据字和包括签名数据块的签名数据模式之间的完全匹配。 IPS通过网络接口接收对象数据字，然后进行部分匹配确定，其中两个或更多个但少于所有主题数据块分别与存储在部分匹配中的相同数量的签名数据块匹配硬件相对于价值和位置。此后，IPS进行完全匹配确定，即所有主题数据块分别与存储在IPS的全匹配硬件中的所有签名数据块相对于值和位置相匹配。然后，IPS存储已经进行完全匹配确定的指示符，并且还可以执行一个或多个另外的入侵防止响应。

10. 发明授权

US07954034B1 Method of and system for protecting data during conversion from an ECC protection scheme to a parity protection scheme 有权
标题翻译：在从ECC保护方案转换为奇偶校验保护方案期间保护数据的方法和系统
公开(公告)号：US07954034B1
公开(公告)日：2011-05-31
申请号：US11241167
申请日：2005-09-30
申请人： Clayton A. Curry , Brian K. Campbell
发明人： Clayton A. Curry , Brian K. Campbell
IPC分类号： H03M13/00
CPC分类号： H03M13/13 , H03M13/3776
摘要： A method of protecting data during transmission from an ECC protection scheme to a parity protection scheme, including reading a data word and an associated ECC from an upstream device; generating parity for the data word; generating a new ECC from the data word; computing a syndrome of the associated ECC and the new ECC; determining, based on the syndrome, if an error is present in the data word or the associated ECC; correcting a correctable error in the data word; correcting the parity for the data word; and transmitting the corrected data word and the corrected parity for the data word to a downstream device.
摘要翻译：一种在从ECC保护方案到奇偶保护方案的传输期间保护数据的方法，包括从上游装置读取数据字和相关联的ECC; 产生数据字的奇偶校验; 从数据字生成新的ECC; 计算相关ECC和新ECC的综合征; 基于所述综合征确定所述数据字或相关ECC中是否存在错误; 纠正数据字中的可纠正错误; 纠正数据字的奇偶校验; 并将修正的数据字和用于数据字的校正奇偶校验发送到下游设备。

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