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1. 发明授权

US4494150A Word autocorrelation redundancy match facsimile compression for text processing systems 失效
标题翻译：字自相关冗余匹配文本处理系统的传真压缩
公开(公告)号：US4494150A
公开(公告)日：1985-01-15
申请号：US397704
申请日：1982-07-13
申请人： Norman F. Brickman , Walter S. Rosenbaum
发明人： Norman F. Brickman , Walter S. Rosenbaum
IPC分类号： H04N1/21 , H03M7/42 , H03M7/48 , H04N1/00 , H04N1/411 , H04N7/12
CPC分类号： H04N1/4115 , H03M7/42 , H03M7/48
摘要： A method and system for compacting text data to be transmitted over communications lines and thereby reduce the data volume and transmission time. Transmitting and receiving text processing systems are provided identical library memories containing text strings such as words commonly used in correspondence. Each word in a document to be communicated is compared to the transmitting system's word library and, if found in the library, only the library address is transmitted. If the word is not found in the library, then it is added to the transmitting system's library, sent, and added to the receiving system's library. The receiving system reconstructs the document by using the received addresses to access the appropriate words from its library and place them in the document. The system combines this word match encoding with character match encoding and facsimile run length encoding for communicating words not found in the system library.
摘要翻译：一种用于压缩通过通信线路发送的文本数据从而减少数据量和传输时间的方法和系统。发送和接收文本处理系统提供了相同的库存储器，其包含文本串，例如通信中通常使用的单词。将要传送的文档中的每个单词与发送系统的单词库进行比较，如果在库中找到，则仅传输库地址。如果在库中找不到该字，则将其添加到发送系统的库中，发送并添加到接收系统的库中。接收系统通过使用接收到的地址来重构文档，以从其库中访问适当的单词并将它们放在文档中。该系统将该字匹配编码与字符匹配编码和传真运行长度编码相结合，用于传达在系统库中未发现的单词。

2. 发明授权

US4499499A Method for identification and compression of facsimile symbols in text processing systems 失效
标题翻译：文本处理系统中传真符号的识别和压缩方法
公开(公告)号：US4499499A
公开(公告)日：1985-02-12
申请号：US454230
申请日：1982-12-29
申请人： Norman F. Brickman , Walter S. Rosenbaum
发明人： Norman F. Brickman , Walter S. Rosenbaum
IPC分类号： H04N1/00 , G06K9/80 , G06T9/00 , H04N1/41 , H04N1/411 , H04N1/40
CPC分类号： G06K9/80 , H04N1/4115
摘要： An improved system for identifying and compacting text data to be transmitted over communications lines and thereby reducing the data volume and transmission time. Transmitting and receiving text processing systems are provided identical library memories containing words commonly used in correspondence. Each word in a document to be communicated is compared to the transmitting system's word library and, if found in the library, only the library address is transmitted. If the word is not found in the library, then it is added to the transmitting system's library, sent, and added to the receiving system's library. The receiving system reconstructs the document by using the received addresses to access the appropriate words from its library and place them in the document. The system combines this word match encoding with character match encoding and facsimile run length encoding for communicating words not found in the system library. The character match process requires a template match and non-linear difference code summation combined with N-dimensional weighting using prestored feature vectors for statistically determining the match between an input character and characters stored in the system library.
摘要翻译：一种改进的系统，用于识别和压缩通过通信线路发送的文本数据，从而减少数据量和传输时间。发送和接收文本处理系统提供了包含通信中通常使用的单词的相同的库存储器。将要传送的文档中的每个单词与发送系统的单词库进行比较，如果在库中找到，则仅传输库地址。如果在库中找不到该字，则将其添加到发送系统的库中，发送并添加到接收系统的库中。接收系统通过使用接收到的地址来重构文档，以从其库中访问适当的单词并将它们放在文档中。该系统将该字匹配编码与字符匹配编码和传真运行长度编码相结合，用于传达在系统库中未发现的单词。字符匹配过程需要模板匹配和非线性差分代码求和与使用预存的特征向量的N维加权相结合，以统计确定输入字符与存储在系统库中的字符之间的匹配。

3. 发明授权

US4307461A Call processor for a satellite communications controller 失效
公开(公告)号：US4307461A
公开(公告)日：1981-12-22
申请号：US133733
申请日：1980-03-25
申请人： Norman F. Brickman , William R. Crosthwait
发明人： Norman F. Brickman , William R. Crosthwait
IPC分类号： H04Q3/545 , H04B7/15 , H04B7/212 , H04J3/00 , H04Q11/04 , H04M3/00 , G06F3/04 , H04J3/02
CPC分类号： H04Q11/0407
摘要： A call processor is disclosed for a satellite communications controller, having a plurality of M voice ports, with an E lead input and an M lead output connected to each of a first subplurality of voice ports for rotary dial telephones, a tone digit interface connected to each of a second subplurality of voice ports which are dedicated to transducing a tone digit received from a multifrequency dialing telephone which is connected to one of a third plurality of voice ports. The third voice ports are connected by means of an intranodal wrap through a digital switch in the communications controller with the transducing circuits at the second voice ports so that the transducing circuitry can be shared among all of the third plurality of voice ports connected to multifrequency dialing telephones. The call processor employs a substantial amount of processing logic in the form of clocked control logic which is executed in a nested time slice operation. The call processor includes a timing circuit having a first output for generating N periodic logic intervals in M periodic port scanning intervals generated at a second output thereof. The call processor includes a port status buffer having an address input connected to the second output of the timer, for storing a plurality of M-PSB words. Each PSB word stores the current status of a corresponding one of the M voice ports as a control state, the E&M lead states, processor communication status, state time duration, and a dialing digit. The clocked control logic has an input register connected to a data output of the port status buffer for receiving the PSB words as they are accessed sequentially from locations in the port status buffer. The clocked control logic has a modulo N counter connected to the first output of the timer, for sequencing clocked logiccontrol operations having combinatorial logic block inputs connected to the input register and the modulo N counter. The clocked logic control operations are executed in response to the counter, to selectively modify portions of the PSB word. The selectively modified PSB word is then rewritten into the port status buffer at the location accessed by the second output of the timer. Incrementing and decrementing logic operating synchronously with the counter, selectively modifies the state time duration field and dialing digit field in response to the clocked logic control operations. After control states embodied in the clocked control logic have completed their function, the results of the operation are transmitted to the host processor to complete the call connection operations in the satellite communications controller. The use of clocked control logic which is shared on a nested, time slice basis among all of the M voice ports enables the call processor to handle a large number of calls simultaneously while relieving the host processor of the management tasks associated with carrying out these call processing functions.

4. 发明授权

US4551835A X.21 Switching system 失效
标题翻译： X.21切换系统
公开(公告)号：US4551835A
公开(公告)日：1985-11-05
申请号：US508312
申请日：1983-06-27
申请人： Joseph M. Bensadon , Norman F. Brickman
发明人： Joseph M. Bensadon , Norman F. Brickman
IPC分类号： H04L29/02 , H04B7/15 , H04B7/212 , H04Q11/04 , H04J3/12
CPC分类号： H04B7/212
摘要： A system is disclosed to provide X.21 in-band call establishment signaling in the data path of a data communication system by utilizing a data port, digital switch and telephone signaling call processor in a satellite communications controller. The system includes an X.21 signaling protocol between a DTE and the satellite communications controller on the terrestrial side and allows self-switched digital data port functions in lieu of associated voice port and line functions as practiced in the prior art. An important aspect is that the signaling rate is the same as the line data rate. The data port goes through three generalized states during a normal call process. The first general state is idle, the second general state is the signaling state and the third general state is the data transfer state. At the start of the signaling state, the E input to the call processor is activated for the appropriate port. Call establishment signals are then processed through the digital switch and an X.21 adapter to the system's control processor. In the third data transfer state, the call establishment signaling has been completed and all data bits go through the digital switch and are transmitted to the digital interface. At the end of the call the data port goes back to the first, idle state.The significant overall feature of the system is the provision for X.21 in-band signaling on the terrestrial side of the satellite communications controller so that a digital data port can accept X.21 in-band call processing type signals. The digital data port detects the call processing type signals with the X.21 protocol and passes them on to the X.21 adapter in the satellite communications controller.
摘要翻译：公开了一种通过利用卫星通信控制器中的数据端口，数字交换机和电话信令呼叫处理器在数据通信系统的数据路径中提供X.21带内呼叫建立信令的系统。该系统包括在DTE和地面上的卫星通信控制器之间的X.21信令协议，并允许自交换数字数据端口功能代替现有技术中实现的相关语音端口和线路功能。一个重要的方面是信令速率与线路数据速率相同。在正常呼叫过程中，数据端口经历三种广义状态。第一个一般状态是空闲的，第二个一般状态是信令状态，第三个一般状态是数据传输状态。在信令状态开始时，呼叫处理器的E输入被激活用于适当的端口。然后通过数字交换机处理呼叫建立信号，并将X.21适配器处理到系统的控制处理器。在第三数据传输状态中，呼叫建立信令已经完成，并且所有数据比特都经过数字交换机并被发送到数字接口。在呼叫结束时，数据端口返回到第一个空闲状态。该系统的重要整体特征是在卫星通信控制器的地面侧提供X.21带内信令，使得数字数据端口可以接受X.21带内呼叫处理类型信号。数字数据端口使用X.21协议检测呼叫处理类型信号，并将其传递到卫星通信控制器中的X.21适配器。

5. 发明授权

US4315330A Multiple data rate testing of communication equipment 失效
标题翻译：通信设备的多重数据速率测试
公开(公告)号：US4315330A
公开(公告)日：1982-02-09
申请号：US128057
申请日：1980-03-07
申请人： Norman F. Brickman , Bruno R. Graziano
发明人： Norman F. Brickman , Bruno R. Graziano
IPC分类号： H04J3/00 , H04B7/15 , H04B17/00 , H04J3/14 , H04Q11/04
CPC分类号： H04J3/14
摘要： The invention finds application in a TDMA communications controller having a plurality of i input/output ports. The input/output ports transfer data from respective, local data users to a transmit bus and transfer data from a receive bus to respective local users on a time interleaved basis during periodic TDMA frames. Each port operates at its own data rate R.sub.i, with data ports having different data rates in the controller. The invention includes a test card which has a read-only memory (ROM) for storing test patterns for each of the data rates R.sub.i. The test card further includes a random access memory (RAM) having an input connected to the ROM, for storing one of the test patterns from the ROM. The test card further includes a processor having control outputs to the RAM and the ROM for controlling the transfer of one of the test patterns from the ROM to the RAM for the data rate R.sub.j of the data port under test. The test card further includes a direct memory access (DMA) control connected between a data output from the RAM and the transmit bus and connected between a data input to the RAM and the receive bus.
摘要翻译：本发明应用于具有多个i输入/输出端口的TDMA通信控制器中。在周期性TDMA帧期间，输入/输出端口将数据从相应的本地数据用户传送到发送总线，并且在时间交织的基础上将数据从接收总线传送到各个本地用户。每个端口以其自己的数据速率Ri运行，数据端口在控制器中具有不同的数据速率。本发明包括测试卡，该测试卡具有用于存储每个数据速率Ri的测试模式的只读存储器（ROM）。测试卡还包括具有连接到ROM的输入的随机存取存储器（RAM），用于从ROM存储测试模式之一。测试卡还包括具有到RAM和ROM的控制输出的处理器，用于控制用于测试数据端口的数据速率Rj的从ROM到RAM的测试模式之一的传送。测试卡还包括连接在从RAM输出的数据和发送总线之间并连接到输入到RAM的数据和接收总线之间的直接存储器访问（DMA）控制。

6. 发明授权

US4320504A Mechanism for synchronization of data ports in TDMA communication 失效
标题翻译： TDMA通信中数据端口同步的机制
公开(公告)号：US4320504A
公开(公告)日：1982-03-16
申请号：US128321
申请日：1980-03-07
申请人： Joseph A. Alvarez, III , Joseph M. Bensadon , John F. Brennen , Norman F. Brickman , Robert W. Krug
发明人： Joseph A. Alvarez, III , Joseph M. Bensadon , John F. Brennen , Norman F. Brickman , Robert W. Krug
IPC分类号： H04J3/06 , H04B7/15 , H04B7/185 , H04B7/212 , H04B7/26 , H04L23/00 , H04J3/16
CPC分类号： H04B7/18523 , H04B7/2643
摘要： The transmission and reception pattern generators are synchronized for all data ports operating at the same data rate throughout an entire TDMA system. This eliminates the necessity for bit stuffing to accommodate non-integral multiple data rate data ports and yet allows data activity compression operations to be carried out.
摘要翻译：对于在整个TDMA系统中以相同数据速率工作的所有数据端口，发送和接收模式发生器被同步。这消除了对位填充以适应非整数多个数据速率数据端口的必要性，并且允许执行数据活动压缩操作。

7. 发明授权

US5513298A Instantaneous context switching for speech recognition systems 失效
标题翻译：语音识别系统的瞬时上下文切换
公开(公告)号：US5513298A
公开(公告)日：1996-04-30
申请号：US443685
申请日：1995-05-18
申请人： Vince M. Stanford , Alice G. Klein , Norman F. Brickman
发明人： Vince M. Stanford , Alice G. Klein , Norman F. Brickman
IPC分类号： G06F3/16 , G10L15/06 , G10L15/10 , G10L15/14 , G10L15/18 , G10L15/26 , G10L9/00
CPC分类号： G06F3/16 , G10L15/06 , G10L15/10 , G10L15/18 , G10L15/26 , G10L15/14 , G10L15/142 , G10L15/197
摘要： An instantaneous context switching speech recognition system is disclosed which enables a speech recognition application to be changed without loading new pattern matching data into the system. Selectable pointer maps are included in the memory of the system which selectively change the relationship between words and phonemes between a first application context and the pattern matching logic to a second application context and the pattern matching logic.
摘要翻译：公开了一种瞬时上下文切换语音识别系统，其能够在不将新的模式匹配数据加载到系统中的情况下改变语音识别应用。可选择的指针图包括在系统的存储器中，其选择性地将第一应用上下文和模式匹配逻辑之间的字和音素之间的关系改变为第二应用上下文和模式匹配逻辑。

8. 发明授权

US5475792A Telephony channel simulator for speech recognition application 失效
标题翻译：用于语音识别应用的电话通道模拟器
公开(公告)号：US5475792A
公开(公告)日：1995-12-12
申请号：US201157
申请日：1994-02-24
申请人： Vince M. Stanford , Norman F. Brickman
发明人： Vince M. Stanford , Norman F. Brickman
IPC分类号： G06F3/16 , G10L15/00 , G10L15/02 , G10L15/06 , G10L15/14 , G10L15/20 , G10L19/00 , H04B14/04 , G01L9/00
CPC分类号： G10L15/063 , G10L15/142 , G10L15/20 , G10L25/06 , G10L25/24
摘要： A telephony channel simulation process is disclosed for training a speech recognizer to respond to speech obtained from telephone systems. An input speech data set is provided to a speech recognition training processor, whose bandwidth is higher than a telephone bandwidth. The process performs a series of alterations to the input speech data set to obtain a modified speech data set. The modified speech data set enables the speech recognition processor to perform speech recognition on voice signals from a telephone system.
摘要翻译：公开了一种用于训练语音识别器以响应从电话系统获得的语音的电话信道模拟过程。将输入语音数据集提供给其带宽高于电话带宽的语音识别训练处理器。该过程对输入语音数据集执行一系列改变以获得修改的语音数据集。经修改的语音数据集使得语音识别处理器能够对来自电话系统的语音信号执行语音识别。

9. 发明授权

US4328543A Control architecture for a communications controller 失效
公开(公告)号：US4328543A
公开(公告)日：1982-05-04
申请号：US133734
申请日：1980-03-25
申请人： Norman F. Brickman , Earl J. McDonald
发明人： Norman F. Brickman , Earl J. McDonald
IPC分类号： H04J3/00 , G06F3/00 , G06F13/00 , H04B7/14 , H04B7/15 , H04B7/212 , H04L13/00 , H04L29/04 , G06F15/20
CPC分类号： G06F3/00 , G06F13/00 , H04B7/14 , H04B7/15 , H04B7/212 , H04J3/00 , H04L13/00 , H04L29/04
摘要： A control architecture is disclosed for a communications controller, for connecting a control processor in the communications controller to a plurality of internal processing subunits which operate asynchronously at different data rates. The architecture includes a control adapter which is connected between the control processor and a common subunit bus, for receiving from the control processor, a control command, a plurality of data words, and an associated address for a respective one of the processing subunits. The control adapter outputs an operating code and the plurality of data words on the common subunit bus and further outputs a subunit select signal on a respective subunit select line to the subunit designated in the address. The adapter further includes a memory for storing the number of shift intervals to be applied to a stack shift signal which is output on a stack shift bus which is common to all of the subunits. The architecture further includes a register stack in each of the processing subunits, having a data input connected to the common subunit bus and a select input connected to the respective subunit select lines from the adapter. Each selected register stack will serially shift and store the operating code and each of the plurality of data words from the common bus, into respective stages of the register stack. The architecture further includes an operating code decoder in each of the processing subunits, having an input connected to one of the stages in its respective register stack, for executing the operating code in the processing subunit. The selected processing subunit reads the plurality of data words from its register stack stages in parallel in response to an output from the operating code decoder. In this manner, a uniform interface between the control processor and the plurality of processing subunits is achieved. The control architecture further includes a timer in the control adapter, having a stored, predetermined execution period associated with each of the processing subunits. A device stack output enable bus is output from the adapter and is common to all of the subunits, for enabling the shifting of data stored in the register stack of the selected one of the subunits to be serially read out to the common bus in response to the predetermined number of shift intervals for that subunit. In this manner, data can be selectively read from each of the subunits without regard for its asynchronous operation.

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