专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070180213A1 Memory construction apparatus 失效
标题翻译：记忆构造装置
公开(公告)号：US20070180213A1
公开(公告)日：2007-08-02
申请号：US11698856
申请日：2007-01-29
申请人： Noritoshi Yamakawa , Hiroaki Miyamoto , Yoshikatsu Kouhara , Akitsugu Nakayama , Kouichi Tanda
发明人： Noritoshi Yamakawa , Hiroaki Miyamoto , Yoshikatsu Kouhara , Akitsugu Nakayama , Kouichi Tanda
IPC分类号： G06F12/00
CPC分类号： G06F17/505
摘要： A memory construction apparatus for automatically forming a logical memory space, thereby making it possible to design an integrated circuit efficiently. A logical memory construction-processing section reads several kinds of physical memories and registers prepared in advance as libraries, generates candidates for each logical memory, by combining only the physical memories or only the registers, or both the physical memories and the registers, with each other, so as to construct the logical memory that satisfies a logical conditions defining a memory space, and selects highest priority candidates for the logical memories from the candidates according to priorities. An optimum construction extraction-processing section extracts optimum logical memories satisfying the respective logical conditions from the highest priority candidates such that the limit numbers of usable physical memories and usable registers are satisfied. A circuit description-processing section executes circuit description by using the physical memories and the registers that construct each of the extracted optimum logical memories, to thereby generate a circuit description file.
摘要翻译：一种用于自动形成逻辑存储器空间的存储器构造装置，从而可以有效地设计集成电路。逻辑存储器构造处理部分读取作为库预先准备的几种物理存储器和寄存器，通过仅结合物理存储器或仅存储寄存器或物理存储器和寄存器两者来产生每个逻辑存储器的候选，每个构成满足定义存储器空间的逻辑条件的逻辑存储器，根据优先级从候选中选择逻辑存储器的最高优先级候选。最佳构造提取处理部分从最高优先级候选中提取满足各个逻辑条件的最佳逻辑存储器，使得满足可用物理存储器和可用寄存器的限制数量。电路描述处理部分通过使用构成每个提取的最佳逻辑存储器的物理存储器和寄存器来执行电路描述，从而生成电路描述文件。

2. 发明授权

US07805688B2 Memory construction apparatus for forming logical memory space 失效
标题翻译：用于形成逻辑存储空间的存储器构造装置
公开(公告)号：US07805688B2
公开(公告)日：2010-09-28
申请号：US11698856
申请日：2007-01-29
申请人： Noritoshi Yamakawa , Hiroaki Miyamoto , Yoshikatsu Kouhara , Akitsugu Nakayama , Kouichi Tanda
发明人： Noritoshi Yamakawa , Hiroaki Miyamoto , Yoshikatsu Kouhara , Akitsugu Nakayama , Kouichi Tanda
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A logical memory construction-processing section reads several kinds of physical memories and registers prepared in advance as libraries, generates candidates for each logical memory, by combining only the physical memories or only the registers, or both the physical memories and the registers, with each other, so as to construct the logical memory that satisfies a logical condition defining a memory space, and selects highest priority candidates for the logical memories from the candidates according to priorities. An optimum construction extraction-processing section extracts optimum logical memories satisfying the respective logical conditions from the highest priority candidates such that the limit numbers of usable physical memories and usable registers are satisfied. A circuit description-processing section executes circuit description by using the physical memories and the registers that construct each of the extracted optimum logical memories, to thereby generate a circuit description file.
摘要翻译：逻辑存储器构造处理部分读取作为库预先准备的几种物理存储器和寄存器，通过仅结合物理存储器或仅存储寄存器或物理存储器和寄存器两者来产生每个逻辑存储器的候选，每个构成满足定义存储器空间的逻辑条件的逻辑存储器，并且根据优先级从候选中选择逻辑存储器的最高优先级候选。最佳构造提取处理部分从最高优先级候选中提取满足各个逻辑条件的最佳逻辑存储器，使得满足可用物理存储器和可用寄存器的限制数量。电路描述处理部分通过使用构成每个提取的最佳逻辑存储器的物理存储器和寄存器来执行电路描述，从而生成电路描述文件。

3. 发明授权

US07735028B2 Logic circuit redesign program, logic circuit redesign apparatus, and logic circuit redesign method 失效
标题翻译：逻辑电路重新设计程序，逻辑电路重新设计装置和逻辑电路重新设计方法
公开(公告)号：US07735028B2
公开(公告)日：2010-06-08
申请号：US11902050
申请日：2007-09-18
申请人： Yoshinori Soejima , Yoshikatsu Kouhara , Hiroaki Shiraishi , Kouichi Tanda , Takakazu Tokunaga , Koji Takatomi
发明人： Yoshinori Soejima , Yoshikatsu Kouhara , Hiroaki Shiraishi , Kouichi Tanda , Takakazu Tokunaga , Koji Takatomi
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A computer is allowed to execute an information acquisition process that acquires a file expressing information on pins used in respective ports provided in each block of a logic circuit to be redesigned and information indicating connection relationships between the ports (#2); execute a multiplexer disposition process that, based on the file, classifies pins of output ports of a block into a number of pin groups that is less than the number of pins, and disposes a multiplexer having a function to multiplex a signal output from each pin classified in the same pin group (#11, #13); and execute a demultiplexer disposition process that, based on that file, disposes a demultiplexer having a function to demultiplex signals that have been output from output ports of a block and multiplexed by the multiplexer, and a function to output each demultiplexed signal to input ports of respective input destination blocks (#12, #13).
摘要翻译：允许计算机执行信息获取处理，获取表示在要重新设计的逻辑电路的每个块中提供的相应端口中使用的引脚的信息的文件和指示端口之间的连接关系的信息（＃2）。执行多路复用器配置处理，其基于该文件，将块的输出端口的引脚分成小于引脚数的多个引脚组，并且配置具有复用从每个引脚输出的信号的功能的多路复用器分为同一个针脚组（＃11，＃13）; 并且执行解复用器配置处理，其基于该文件，配置具有从多路复用器的多路复用器的多路复用器多路复用的多路复用器的输出端口输出的多路复用功能的解复用器，以及将各解复用信号输出到各个输入目的地块（＃12，＃13）。

4. 发明申请

US20070217444A1 Computer 审中-公开
标题翻译：电脑
公开(公告)号：US20070217444A1
公开(公告)日：2007-09-20
申请号：US11711806
申请日：2007-02-28
申请人： Yoshikatsu Kouhara , Yoshinori Soejima , Hiroaki Shiraishi , Kouichi Tanda , Takakazu Tokunaga
发明人： Yoshikatsu Kouhara , Yoshinori Soejima , Hiroaki Shiraishi , Kouichi Tanda , Takakazu Tokunaga
IPC分类号： H04L12/66
CPC分类号： G06F17/5045
摘要： A computer capable of easily obtaining RTL of a TOP circuit after a block circuit is separated out of the TOP circuit. A port information input unit inputs the port information of the TOP circuit described in RTL, and the port information of block circuits composing the TOP circuit, from a user. A separation information input unit inputs separation information specifying a block circuit to be separated out of the TOP circuit, from the user. A separation port information creation unit creates separation port information after the block circuit is separated, by changing the port information of the TOP circuit and the block circuits based on the port information of the block circuit to be separated according to the separation information. An RTL rewriting unit rewrites RTL of the TOP circuit from which the block circuit has been separated, based on the separation port information created by the separation port information creation unit.
摘要翻译：能够在块电路之后容易地获得TOP电路的RTL的计算机从TOP电路分离出来。端口信息输入单元从用户输入RTL中描述的TOP电路的端口信息和构成TOP电路的块电路的端口信息。分离信息输入单元从用户输入指定要从TOP电路分离的块电路的分离信息。分离端口信息创建单元通过根据分离信息根据要分离的块电路的端口信息改变TOP电路和块电路的端口信息，在块电路分离之后创建分离端口信息。 RTL重写单元基于由分离端口信息创建单元创建的分离端口信息重写已经从块电路分离的TOP电路的RTL。

5. 发明申请

US20080077904A1 Logic circuit redesign program, logic circuit redesign apparatus, and logic circuit redesign method 失效
标题翻译：逻辑电路重新设计程序，逻辑电路重新设计装置和逻辑电路重新设计方法
公开(公告)号：US20080077904A1
公开(公告)日：2008-03-27
申请号：US11902050
申请日：2007-09-18
申请人： Yoshinori Soejima , Yoshikatsu Kouhara , Hiroaki Shiraishi , Kouichi Tanda , Takakazu Tokunaga , Koji Takatomi
发明人： Yoshinori Soejima , Yoshikatsu Kouhara , Hiroaki Shiraishi , Kouichi Tanda , Takakazu Tokunaga , Koji Takatomi
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A computer is allowed to execute an information acquisition process that acquires a file expressing information on pins used in respective ports provided in each block of a logic circuit to be redesigned and information indicating connection relationships between the ports (#2); execute a multiplexer disposition process that, based on the file, classifies pins of output ports of a block into a number of pin groups that is less than the number of pins, and disposes a multiplexer having a function to multiplex a signal output from each pin classified in the same pin group (#11, #13); and execute a demultiplexer disposition process that, based on that file, disposes a demultiplexer having a function to demultiplex signals that have been output from output ports of a block and multiplexed by the multiplexer, and a function to output each demultiplexed signal to input ports of respective input destination blocks (#12, #13).
摘要翻译：允许计算机执行信息获取处理，获取表示在要重新设计的逻辑电路的每个块中提供的相应端口中使用的引脚的信息的文件和指示端口之间的连接关系的信息（＃2）。执行多路复用器配置处理，其基于该文件，将块的输出端口的引脚分成小于引脚数的多个引脚组，并且配置具有复用从每个引脚输出的信号的功能的多路复用器分为同一个针脚组（＃11，＃13）; 并且执行解复用器配置处理，其基于该文件，配置具有对多路复用器的多路复用器多路复用的多路复用器的输出端口输出的信号进行解复用的解复用器，以及将各解复用信号输出到各个输入目的地块（＃12，＃13）。

6. 发明授权

US07761822B2 File information generating method, file information generating apparatus, and storage medium storing file information generation program 失效
标题翻译：文件信息生成方法，文件信息生成装置以及存储文件信息生成程序的存储介质
公开(公告)号：US07761822B2
公开(公告)日：2010-07-20
申请号：US12048668
申请日：2008-03-14
申请人： Koji Takatomi , Kouichi Tanda , Hiroaki Shiraishi , Yoshikatsu Kouhara , Takakazu Tokunaga
发明人： Koji Takatomi , Kouichi Tanda , Hiroaki Shiraishi , Yoshikatsu Kouhara , Takakazu Tokunaga
IPC分类号： G06F17/50
CPC分类号： G06F17/30067
摘要： A method and apparatus for generating file information including setting clock information regarding a clock condition and a clock speed to be used by a speed conversion circuit block, reconstructing the clock circuit block including a new clock for accommodating insertion of the speed conversion circuit block, and associating connection terminal information indicating a connection relationship of connection terminals with speed conversion object information having set, as a speed conversion object, a connection terminal requiring connection speed conversion. The connection terminal information of the connection terminal set as the speed conversion object is extracted, speed conversion circuit information indicating a connection relationship of the connection terminals in the speed conversion circuit block and connection terminal information having the connection relationship of the connection terminals reconstructed is generated, and file information in which the speed conversion circuit block is inserted between the clock circuit block and the interface block is generated.
摘要翻译：一种用于产生文件信息的方法和装置，包括设置有关速度转换电路块使用的时钟条件和时钟速度的时钟信息，重构包括用于容纳插入速度转换电路块的新时钟的时钟电路块，以及将表示连接终端的连接关系的连接终端信息与具有设定的速度转换对象信息相关联，作为速度转换对象，需要连接速度转换的连接终端。提取设置为速度转换对象的连接终端的连接终端信息，生成指示速度转换电路块中的连接端子的连接关系的速度转换电路信息和重建连接端子的连接关系的连接终端信息，并且生成在时钟电路块和接口块之间插入速度转换电路块的文件信息。

7. 发明授权

US08078423B2 Data generating method, connection checking system, and computer product 有权
标题翻译：数据生成方法，连接检查系统和计算机产品
公开(公告)号：US08078423B2
公开(公告)日：2011-12-13
申请号：US11859040
申请日：2007-09-21
申请人： Takakazu Tokunaga , Kouichi Tanda , Hiroaki Shiraishi , Yoshikatsu Kouhara , Koji Takatomi
发明人： Takakazu Tokunaga , Kouichi Tanda , Hiroaki Shiraishi , Yoshikatsu Kouhara , Koji Takatomi
IPC分类号： G01R31/3183
CPC分类号： G01R31/318516 , G01R31/31717
摘要： A computer terminal retrieves pin data related to respective pins of a plurality of Field Programmable Gate Array that are mounted on a board. The computer terminal retrieves setting data related to a connection check. Upon retrieving the pin data and the setting data, the computer terminal assigns, as data for the connection check to all the pins that can output data, unique data that is unique to each pin. The computer terminal generates input pin data and output pin data containing the unique data, stores therein the input pin data and the output pin data, and generates checking circuits that check connections between output pins and input pins. The computer terminal generates checking data based on the checking circuits.
摘要翻译：计算机终端检索与安装在电路板上的多个现场可编程门阵列的相应引脚相关的引脚数据。计算机终端检索与连接检查相关的设置数据。在检索引脚数据和设置数据后，计算机终端将连接检查的数据分配给可输出数据的所有引脚，每个引脚唯一的唯一数据。计算机终端产生输入引脚数据并输出包含唯一数据的引脚数据，在其中存储输入引脚数据和输出引脚数据，并产生检查输出引脚和输入引脚之间的连接的检查电路。计算机终端根据检查电路生成检查数据。

8. 发明申请

US20080235530A1 FILE INFORMATION GENERATING METHOD, FILE INFORMATION GENERATING APPARATUS, AND STORAGE MEDIUM STORING FILE INFORMATION GENERATION PROGRAM 失效
标题翻译：文件信息生成方法，文件信息生成装置和存储介质存储文件信息生成程序
公开(公告)号：US20080235530A1
公开(公告)日：2008-09-25
申请号：US12048668
申请日：2008-03-14
申请人： Koji Takatomi , Kouichi Tanda , Hiroaki Shiraishi , Yoshikatsu Kouhara , Takakazu Tokunaga
发明人： Koji Takatomi , Kouichi Tanda , Hiroaki Shiraishi , Yoshikatsu Kouhara , Takakazu Tokunaga
IPC分类号： G06F1/08
CPC分类号： G06F17/30067
摘要： A method and apparatus for generating file information including setting clock information regarding a clock condition and a clock speed to be used by a speed conversion circuit block, reconstructing the clock circuit block including a new clock for accommodating insertion of the speed conversion circuit block, and associating connection terminal information indicating a connection relationship of connection terminals with speed conversion object information having set, as a speed conversion object, a connection terminal requiring connection speed conversion. The connection terminal information of the connection terminal set as the speed conversion object is extracted, speed conversion circuit information indicating a connection relationship of the connection terminals in the speed conversion circuit block and connection terminal information having the connection relationship of the connection terminals reconstructed is generated, and file information in which the speed conversion circuit block is inserted between the clock circuit block and the interface block is generated.
摘要翻译：一种用于产生文件信息的方法和装置，包括设置有关速度转换电路块使用的时钟条件和时钟速度的时钟信息，重构包括用于容纳插入速度转换电路块的新时钟的时钟电路块，以及将表示连接终端的连接关系的连接终端信息与具有设定的速度转换对象信息相关联，作为速度转换对象，需要连接速度转换的连接终端。提取设置为速度转换对象的连接终端的连接终端信息，生成指示速度转换电路块中的连接端子的连接关系的速度转换电路信息和重建连接端子的连接关系的连接终端信息，并且生成在时钟电路块和接口块之间插入速度转换电路块的文件信息。

9. 发明申请

US20080097717A1 DATA GENERATING METHOD, CONNECTION CHECKING SYSTEM, AND COMPUTER PRODUCT 有权
标题翻译：数据生成方法，连接检查系统和计算机产品
公开(公告)号：US20080097717A1
公开(公告)日：2008-04-24
申请号：US11859040
申请日：2007-09-21
申请人： Takakazu Tokunaga , Kouichi Tanda , Hiroaki Shiraishi , Yoshikatsu Kouhara , Koji Takatomi
发明人： Takakazu Tokunaga , Kouichi Tanda , Hiroaki Shiraishi , Yoshikatsu Kouhara , Koji Takatomi
IPC分类号： G01R31/00
CPC分类号： G01R31/318516 , G01R31/31717
摘要： A computer terminal retrieves pin data related to respective pins of a plurality of Field Programmable Gate Array that are mounted on a board. The computer terminal retrieves setting data related to a connection check. Upon retrieving the pin data and the setting data, the computer terminal assigns, as data for the connection check to all the pins that can output data, unique data that is unique to each pin. The computer terminal generates input pin data and output pin data containing the unique data, stores therein the input pin data and the output pin data, and generates checking circuits that check connections between output pins and input pins. The computer terminal generates checking data based on the checking circuits.
摘要翻译：计算机终端检索与安装在电路板上的多个现场可编程门阵列的相应引脚相关的引脚数据。计算机终端检索与连接检查相关的设置数据。在检索引脚数据和设置数据后，计算机终端将连接检查的数据分配给可输出数据的所有引脚，每个引脚唯一的唯一数据。计算机终端产生输入引脚数据并输出包含唯一数据的引脚数据，在其中存储输入引脚数据和输出引脚数据，并产生检查输出引脚和输入引脚之间的连接的检查电路。计算机终端根据检查电路生成检查数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式