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1. 发明授权

US06804074B2 PLL circuit and recording and playback apparatus using same 失效
标题翻译： PLL电路和使用其的记录和播放装置
公开(公告)号：US06804074B2
公开(公告)日：2004-10-12
申请号：US09862422
申请日：2001-05-23
申请人： Norio Shoji , Junkichi Sugita , Kimimasa Senba , Toshihiro Kawakubo
发明人： Norio Shoji , Junkichi Sugita , Kimimasa Senba , Toshihiro Kawakubo
IPC分类号： G11B509
CPC分类号： H03L7/091 , G11B20/1403 , H03L7/14
摘要： A PLL circuit functioning as a clock recovery circuit in a tape recording and playback apparatus employing the PRML method has a level determining circuit for detecting that head output level (signal level) is at or lower than a certain level during track crossing for a high-speed search, and effects a hold on a loop filter according to a level determination output to thereby hold PLL operation, whereby the PLL behavior is not disturbed by a noise component occurring during track crossing. Thus, it is possible to stabilize search operation and increase the design margin.
摘要翻译：在使用PRML方法的磁带记录和重放装置中用作时钟恢复电路的PLL电路具有一个电平确定电路，用于在磁道交叉处检测磁头输出电平（信号电平）等于或低于一定电平，速度搜索，并根据电平确定输出对环路滤波器产生保持，从而保持PLL操作，从而PLL行为不受轨道交叉期间发生的噪声分量的干扰。因此，可以稳定搜索操作并增加设计余量。

2. 发明授权

US06597650B2 Nonlinearity compensation circuit and method, control circuit and method for nonlinearity compenstation circuit and recording and/or playback apparatus employing the same 失效
标题翻译：用于非线性补偿电路的非线性补偿电路和方法，控制电路和方法以及采用该非线性补偿电路的记录和/或重放装置
公开(公告)号：US06597650B2
公开(公告)日：2003-07-22
申请号：US09870714
申请日：2001-06-01
申请人： Masayuki Katakura , Junkichi Sugita , Norio Shoji , Masato Sekine , Kimimasa Senba , Katsuhisa Daio
发明人： Masayuki Katakura , Junkichi Sugita , Norio Shoji , Masato Sekine , Kimimasa Senba , Katsuhisa Daio
IPC分类号： G11B700
CPC分类号： G06G7/24
摘要： A nonlinearity compensation circuit is disclosed which includes an inverse hyperbolic function generation circuit for converting differential currents corresponding to input signals in+ and in− into differential voltages which increase in proportion to an inverse hyperbolic function, an offset provision circuit for providing an offset corresponding to control signals c+ and c− to the differential voltages outputted from the inverse hyperbolic function generation circuit and a hyperbolic function generation circuit for converting the differential voltages to which the offset has been provided by the offset provision circuit into signals which increase in proportion to a hyperbolic function and outputting the resulting signals as output signals out+ and out−. Consequently, compensation for the nonlinearity such as second order distortion can be performed for the read signal from a recording medium.
摘要翻译：公开了一种非线性补偿电路，其包括反相双曲线函数产生电路，用于将对应于+中的输入信号的差分电流转换为与反双曲线函数成比例增加的差分电压;偏移提供电路，用于提供与控制相对应的偏移信号c +和c-对应于从反双曲函数生成电路输出的差分电压，以及双曲线函数生成电路，用于将由偏移提供电路提供的偏移的差分电压转换为与双曲线函数成比例增加的信号并将所得信号作为输出信号out +和out输出。因此，可以对来自记录介质的读取信号执行诸如二阶失真之类的非线性的补偿。

3. 发明授权

US06496076B1 PLL circuit and recorded data reproduction apparatus 有权
标题翻译： PLL电路和记录数据再现装置
公开(公告)号：US06496076B1
公开(公告)日：2002-12-17
申请号：US09717102
申请日：2000-11-22
申请人： Norio Shoji , Kimimasa Senba
发明人： Norio Shoji , Kimimasa Senba
IPC分类号： G11B509
CPC分类号： G11B20/1426 , G11B5/012 , G11B5/09 , H03L7/091
摘要： A PLL (phase-locked loop) circuit is configured with a phase-error detection circuit comprises the following: a provisional judge circuit for provisionally judging a data signal being input to an A/D converter into three levels of 1, 0, and −1; a pattern detector which, among data signals being input in accordance with a result of the provisional judgment, checks a transition pattern ranging from a data signal that precedes one clock cycle to the actually present data signal, and then, when a specific pattern is detected, instructs a selector to select output data from the A/D converter; and the selector which, in compliance with instruction from the pattern detector, selects phase-error data from data signals output from the A/D converter, and then converts the selected phase-error data into an electric current before externally delivering it as an error-current.
摘要翻译： PLL（锁相环）电路配置有一个包括以下的相位误差检测电路：临时判断电路，用于将输入到A / D转换器的数据信号临时判断为三个等级的1,0和 - 1; 在根据临时判断结果输入的数据信号中的模式检测器检查从一个时钟周期之前的数据信号到实际存在的数据信号的转换模式，然后，当检测到特定模式时指示选择器从A / D转换器选择输出数据; 以及选择器，其根据来自模式检测器的指令从从A / D转换器输出的数据信号中选择相位误差数据，然后将所选择的相位误差数据转换为电流，然后将其作为错误传送给外部 -当前。

4. 发明授权

US06693863B2 Asymmetry correcting circuit and information reproducing apparatus using the same 失效
标题翻译：非对称校正电路和使用该不对称校正电路的信息再现装置
公开(公告)号：US06693863B2
公开(公告)日：2004-02-17
申请号：US10122329
申请日：2002-04-16
申请人： Norio Shoji , Yuji Gendai , Kimimasa Senba , Nobuyoshi Kobayashi
发明人： Norio Shoji , Yuji Gendai , Kimimasa Senba , Nobuyoshi Kobayashi
IPC分类号： G11B700
CPC分类号： H03M1/0607 , G11B20/10027 , G11B20/10037 , G11B20/10203 , G11B20/10314 , H03M1/12
摘要： To provide an asymmetry correcting circuit capable of canceling an asymmetry simultaneously with quantization in an ADC and utilizing the dynamic range of the ADC effectively, and also to provide an information reproducing apparatus using such a correcting circuit. An asymmetry correcting circuit includes a first envelope detection circuit for detecting the envelope of a positive peak of an input signal waveform; a second envelope detection circuit for detecting the envelope of a negative peak of the input signal waveform; an adding circuit for producing a sum voltage of the positive peak voltage and the negative peak voltage; a smoothing circuit for smoothing the sum voltage; a multiplying circuit for multiplying the smoothed sum voltage by a predetermined offset adjustment coefficient; and a quantization reference voltage control circuit for DC-wise shifting, in response to the output signal of the multiplying circuit, the median of the quantization reference voltage of the ADC in conformity with the offset derived from the asymmetry of the input signal, and controlling the upper limit and the lower limit of the quantization reference voltage to the values that correspond to the offset quantity.
摘要翻译：提供一种能够在ADC中同时消除不对称性并且有效地利用ADC的动态范围的不对称校正电路，并且还提供使用这种校正电路的信息再现装置。不对称校正电路包括用于检测输入信号波形的正峰值的包络的第一包络检测电路; 第二包络检测电路，用于检测输入信号波形的负峰值的包络; 用于产生正峰值电压和负峰值电压的和电压的加法电路; 平滑电路，用于平滑和电压; 乘法电路，用于将平滑的和电压乘以预定的偏移调整系数; 以及量化参考电压控制电路，用于根据乘法电路的输出信号进行直角移位，ADC的量化参考电压的中值与从输入信号的不对称性导出的偏移一致，并控制量化参考电压的上限和下限对应于偏移量的值。

5. 发明授权

US06683740B1 Architecture for a hard disk drive write amplifier circuit with damping control 失效
标题翻译：具有阻尼控制的硬盘驱动器写放大器电路架构
公开(公告)号：US06683740B1
公开(公告)日：2004-01-27
申请号：US09504160
申请日：2000-02-15
申请人： Soon-Gil Jung , Shang-Ching Dong , Hiroshi Takeuchi , Norio Shoji , Keiji Narusawa , Michiya Sako
发明人： Soon-Gil Jung , Shang-Ching Dong , Hiroshi Takeuchi , Norio Shoji , Keiji Narusawa , Michiya Sako
IPC分类号： G11B502
CPC分类号： G11B5/09 , G11B5/012
摘要： A write amplifier circuit in a magnetic storage system has a cross coupling circuit and an active damp circuit to supply an improved write current to the head writing the data onto the media within the magnetic storage system. The inclusion of the cross coupling circuit decreases a rise time and a fall time associated with the write current. The active damp circuit reduces the undershoot and ringing of the write current. Thus, the write amplifier circuit is suitable for high speed data storage writing applications requiring minimal distortion of the data written to a magnetic medium. The write amplifier circuit achieves these improvements in the waveform of the write current by incorporating circuit elements and using both a negative feedback path and a feedforward path. In particular, the cross coupling circuit provides a feedforward path within the write amplifier circuit to a first current which creates a second current that is proportional and greater than the first current such that the second current increases the write current available for the head. Similarly, the active damp circuit provides a negative feedback path from the output terminals of the write amplifier circuit to a third current which creates a fourth current that is proportional and greater than the third current such that the fourth current damps an undershoot and ringing associated with the write current.
摘要翻译：磁存储系统中的写放大器电路具有交叉耦合电路和有源阻尼电路，用于向磁头提供改善的写入电流，从而将数据写入到磁存储系统内的介质上。交叉耦合电路的包含减少了与写入电流相关联的上升时间和下降时间。有源潮湿电路可以减少写入电流的下冲和振荡。因此，写放大器电路适用于要求写入磁介质的数据失真最小的高速数据存储写入应用。写放大器电路通过并入电路元件并使用负反馈路径和前馈路径来实现写入电流波形的这些改进。特别地，交叉耦合电路将写入放大器电路内的前馈路径提供到第一电流，该第一电流产生比第一电流成比例并且大于第一电流的第二电流，使得第二电流增加可用于磁头的写入电流。类似地，有源阻尼电路提供从写入放大器电路的输出端子到第三电流的负反馈路径，该第三电流产生比第三电流成比例并且大于第三电流的第四电流，使得第四电流抑制下行和与写入电流。

6. 发明申请

US20050179484A1 Bias voltage supply circuit and radio-frequency amplification circuit 失效
标题翻译：偏置电压电路和射频放大电路
公开(公告)号：US20050179484A1
公开(公告)日：2005-08-18
申请号：US11047564
申请日：2005-02-02
申请人： Noboru Sasho , Norio Shoji
发明人： Noboru Sasho , Norio Shoji
IPC分类号： G05F3/26 , G05F3/16 , G05F3/20 , H03F3/19
CPC分类号： G05F3/205
摘要： A bias voltage supply circuit of a radio-frequency amplification circuit has a constant-voltage power supply generating a constant voltage higher than the bias voltage, a rectifier transistor and a constant-current power supply supplying a constant current to the rectifier transistor. The rectifier transistor is connected between a supply point of a bias voltage connected to an input terminal of the radio-frequency amplification transistor via an element for bias supply and a power supply voltage supply line, wherein a control terminal is kept by a constant voltage that the constant-voltage power supply generates. Since descent of electric potential of the input terminal of a radio-frequency signal does not arise because of circuit composition, the radio-frequency amplification circuit has a saturation characteristic superior than a prior art.
摘要翻译：射频放大电路的偏置电压电路具有产生高于偏置电压的恒定电压的恒压电源，整流晶体管和向整流晶体管供给恒定电流的恒流电源。整流晶体管经由用于偏置电源的元件和电源电压供给线连接在与射频放大晶体管的输入端子连接的偏置电压的供电点之间，其中控制端子由恒定电压保持，产生恒压电源。由于电路组成，不产生射频信号的输入端的电位下降，所以射频放大电路的饱和特性优于现有技术。

7. 发明授权

US06762894B2 Head apparatus, hard disk apparatus and recording and playback apparatus 失效
标题翻译：头装置，硬盘装置和记录和重放装置
公开(公告)号：US06762894B2
公开(公告)日：2004-07-13
申请号：US09892999
申请日：2001-06-28
申请人： Keiji Narusawa , Norio Shoji
发明人： Keiji Narusawa , Norio Shoji
IPC分类号： G11B509
CPC分类号： G11B5/012 , G11B5/02 , G11B5/09 , G11B20/10009 , G11B20/24 , G11B33/121 , G11B2005/0013 , G11B2005/0018
摘要： A head apparatus which is tough against disturbing noise and superior in the S/N ratio and which can cope with an increase of the capacity of a recording medium is disclosed. A first playback amplifier for amplifying the playback signal of a MR head and a register circuit for setting the bias current to the MR head are formed as a COS IC. The COS IC is mounted on a suspension together with the MR head. A feeble playback signal outputted from the MR head is amplified by the first playback amplifier once and then transmitted to a mother IC over a pair of signal lines. The amplified playback signal is tough against disturbing noise during transmission.
摘要翻译：公开了一种能够抵抗干扰噪声并且S / N比优异并且能够应付记录介质的容量增加的头装置。形成用于放大MR磁头的重放信号的第一重放放大器和用于将偏置电流设置到MR磁头的寄存器电路作为COS IC。 COS IC与MR头一起安装在悬架上。由MR头输出的微弱重放信号被第一重放放大器放大一次，然后通过一对信号线发送到母IC。放大的播放信号在传输期间对于干扰噪声是坚韧的。

8. 发明授权

US5940952A Method for applying corrosion-protective coating to joint between corrosion-protectively coated steel pipes 失效
标题翻译：在防腐涂层钢管之间对接头施加防腐蚀涂层的方法
公开(公告)号：US5940952A
公开(公告)日：1999-08-24
申请号：US730018
申请日：1996-10-11
申请人： Ryouichi Ikeda , Minoru Komura , Yoshihiro Okano , Norio Shoji , Toshiyuki Namioka , Akio Kida , Kiyotaka Hirahara
发明人： Ryouichi Ikeda , Minoru Komura , Yoshihiro Okano , Norio Shoji , Toshiyuki Namioka , Akio Kida , Kiyotaka Hirahara
IPC分类号： F16L13/02 , B29C61/06 , B29C63/00 , B29C63/42 , B29C65/00 , B29C65/34 , B29C65/68 , F16L11/12 , F16L58/10 , F16L58/18 , H05B3/26 , B23P17/00
CPC分类号： B29C65/68 , B29C61/0625 , B29C63/0047 , B29C63/0091 , B29C63/42 , B29C65/3428 , B29C66/00145 , B29C66/1122 , B29C66/53241 , B29C66/72321 , B29C66/73715 , F16L58/181 , B29C2791/006 , B29C65/3412 , B29C65/3468 , B29C65/3476 , B29C65/3492 , B29C66/71 , B29K2995/0049 , Y10T29/4981 , Y10T29/49888
摘要： A method for applying a corrosion-protective coating, with a heat-shrinkable tube, to a joint between welded end portions of corrosion-protectively coated steel pipes, has a configuration comprising the steps of: preparing a coating implement having a releasant layer formed on the outer circumferential portion of the heat-shrinkable tube, and a heating layer formed on the outer circumferential portion of the releasant layer; positioning the coating implement so as to cover the welded portion of the joint and its adjacent portions; thermally shrinking the coating implement in a state in which the gap between the coating implement and the aforementioned portions is kept in a vacuum; and removing the releasant layer and the heating layer, whereby the aforementioned portions are corrosion-protectively coated by the heat shrinkage of the tube.
摘要翻译：将具有热收缩管的防腐蚀涂层施加到防腐蚀涂层钢管的焊接端部之间的接合处的方法具有以下步骤：制备具有形成在上面的脱模层的涂层工具热收缩管的外周部分和形成在脱离层的外周部分上的加热层; 定位涂层工具以覆盖接头及其相邻部分的焊接部分; 在涂布工具和上述部分之间的间隙保持真空的状态下热收缩涂覆器具; 并且除去上层和加热层，由此上述部分被管的热收缩率腐蚀保护性地涂覆。

9. 发明授权

US6154333A Amplification circuit 有权
标题翻译：放大电路
公开(公告)号：US6154333A
公开(公告)日：2000-11-28
申请号：US213414
申请日：1998-12-17
申请人： Keiji Narusawa , Norio Shoji
发明人： Keiji Narusawa , Norio Shoji
IPC分类号： G11B5/09 , G11B5/00 , G11B5/02 , G11B5/39 , G11B33/12 , H03F3/45
CPC分类号： G11B5/02 , H03F3/45085 , H03F3/45098 , G11B2005/0016 , G11B2005/0018 , G11B33/122 , H03F2203/45458 , H03F2203/45544 , H03F2203/45702
摘要： An amplification circuit for an MR head which can realize a reduction of the power consumption, simplification of the circuit configuration by providing capacitors inside the circuit, and reduction of the number of externally provided parts, wherein a current is supplied to an MR head resistor from a bias current source and the amount of change of the head resistance is converted to a voltage change when reproducing magnetically recorded data. A direct current component of the voltage dropped in the head resistor is cut by capacitors, and only the alternating current component is input to a differential amplification circuit configured by transistors. Recorded data can be distinguished in accordance with an amplified output voltage, so capacitances of direct current cut-off capacitors can be set small and thus the direct current cut-off capacitors can be provided in the IC chip and the number of external parts can be reduced. Furthermore, since the base bias voltages of the transistors are set independently from the MR head, the power consumption can be reduced.
摘要翻译：一种用于MR磁头的放大电路，其可以实现功率消耗的降低，通过在电路内部提供电容器来简化电路配置以及减少外部提供的部件的数量，其中电流被提供给MR头电阻器当再现磁记录数据时，偏置电流源和磁头电阻的变化量被转换为电压变化。头电阻中掉落的电压的直流分量由电容器切断，只有交流分量被输入到由晶体管配置的差分放大电路。可以根据放大的输出电压来区分记录数据，因此可以将直流截止电容器的电容设定得较小，因此可以在IC芯片中提供直流截止电容器，并且可以将外部部件的数量减少此外，由于晶体管的基极偏置电压独立于MR磁头设置，因此可以降低功耗。

10. 发明授权

US6075394A PLL circuit and recording or reproducing apparatus utilizing the same 有权
标题翻译： PLL电路和利用该电路的记录或再现装置
公开(公告)号：US6075394A
公开(公告)日：2000-06-13
申请号：US161953
申请日：1998-09-29
申请人： Norio Shoji
发明人： Norio Shoji
IPC分类号： G11B20/14 , H03L7/089 , H03L7/093 , H03L7/107 , H03L7/06
CPC分类号： H03L7/0805 , H03L7/0893 , H03L7/093 , H03L2207/04 , Y10S331/02
摘要： In a PLL circuit, the phase of the frequency of an input signal is compared with that of an oscillation frequency generated from a voltage-controlled oscillator. Charge pump circuits are provided which outputs currents pulse-width modulated based on information about the error between the two phases, respectively. An output voltage of a capacitor provided at a stage subsequent to one of the charge pump circuits is converted into a current by a gm amplifier. Further, the converted current is added to an output current of the other charge pump circuit. The so-added output is used as a control input for the voltage-controlled oscillator. The oscillation frequency of the voltage-controlled oscillator is produced as an output signal frequency.
摘要翻译：在PLL电路中，将输入信号的频率的相位与从压控振荡器产生的振荡频率的相位进行比较。提供电荷泵电路，其分别基于关于两相之间的误差的信息来输出脉冲宽度调制的电流。设置在一个电荷泵电路之后的级的电容器的输出电压由gm放大器转换成电流。此外，转换的电流被加到另一个电荷泵电路的输出电流。所加的输出用作压控振荡器的控制输入。压控振荡器的振荡频率作为输出信号频率产生。

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