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1. 发明授权

US07244643B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07244643B2
公开(公告)日：2007-07-17
申请号：US10496766
申请日：2002-11-21
申请人： Norio Ishitsuka , Yukihiro Kumagai , Hideo Miura , Shuji Ikeda , Toshifumi Takeda , Hiroyuki Ohta
发明人： Norio Ishitsuka , Yukihiro Kumagai , Hideo Miura , Shuji Ikeda , Toshifumi Takeda , Hiroyuki Ohta
IPC分类号： H01L21/8238
CPC分类号： H01L29/7846 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/7842
摘要： The object of the present invention is to provide a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor, which has a high degree of reliability and excellent drain current characteristics. The gist of the invention for attaining the object resides in disposing a silicon nitride film to the side wall of a trench for an active region in which the n-type channel field effect transistor is formed and disposing the silicon nitride film only in the direction perpendicular to the channel direction to the sidewall of the trench for the active region of the p-type channel field effect transistor. According to the present invention, a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor of excellent current characteristics can be provided.
摘要翻译：本发明的目的是提供一种包括n型沟道场效应晶体管和p型沟道场效应晶体管的半导体器件，其具有高可靠性和优异的漏极电流特性。实现本发明的要点在于，在形成有n型沟道场效应晶体管的有源区的沟槽的侧壁上设置氮化硅膜，仅在垂直方向上设置氮化硅膜到通道方向，到p型沟道场效应晶体管的有源区的沟槽的侧壁。根据本发明，可以提供包括n型沟道场效应晶体管和具有优异电流特性的p型沟道场效应晶体管的半导体器件。

2. 发明申请

US20050121727A1 Semiconductor device and manufacturing method 失效
标题翻译：半导体器件及制造方法
公开(公告)号：US20050121727A1
公开(公告)日：2005-06-09
申请号：US10496766
申请日：2002-11-11
申请人： Norio Ishitsuka , Yukihiro Kumagai , Hideo Miura , Shuji Ikeda , Toshifumi Takeda , Hiroyuki Ohta
发明人： Norio Ishitsuka , Yukihiro Kumagai , Hideo Miura , Shuji Ikeda , Toshifumi Takeda , Hiroyuki Ohta
IPC分类号： H01L21/76 , H01L21/762 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/08 , H01L27/092 , H01L27/10 , H01L29/76 , H01L29/94 , H01L31/113
CPC分类号： H01L29/7846 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/7842
摘要： The object of the present invention is to provide a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor, which has a high degree of reliability and excellent drain current characteristics. The gist of the invention for attaining the object resides in disposing a silicon nitride film to the side wall of a trench for an active region in which the n-type channel field effect transistor is formed and disposing the silicon nitride film only in the direction perpendicular to the channel direction to the sidewall of the trench for the active region of the p-type channel field effect transistor. According to the present invention, a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor of excellent current characteristics can be provided.
摘要翻译：本发明的目的是提供一种包括n型沟道场效应晶体管和p型沟道场效应晶体管的半导体器件，其具有高可靠性和优异的漏极电流特性。实现本发明的要点在于，在形成有n型沟道场效应晶体管的有源区的沟槽的侧壁上设置氮化硅膜，仅在垂直方向上设置氮化硅膜到通道方向，到p型沟道场效应晶体管的有源区的沟槽的侧壁。根据本发明，可以提供包括n型沟道场效应晶体管和具有优异电流特性的p型沟道场效应晶体管的半导体器件。

3. 发明授权

US06982465B2 Semiconductor device with CMOS-field-effect transistors having improved drain current characteristics 有权
标题翻译：具有CMOS场效应晶体管的半导体器件具有改善的漏极电流特性
公开(公告)号：US06982465B2
公开(公告)日：2006-01-03
申请号：US10433786
申请日：2001-12-06
申请人： Yukihiro Kumagai , Hiroyuki Ohta , Fumio Ootsuka , Shuji Ikeda , Takahiro Onai , Hideo Miura , Katsuhiko Ichinose , Toshifumi Takeda
发明人： Yukihiro Kumagai , Hiroyuki Ohta , Fumio Ootsuka , Shuji Ikeda , Takahiro Onai , Hideo Miura , Katsuhiko Ichinose , Toshifumi Takeda
IPC分类号： H01L29/76
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L27/092
摘要： The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics.In a semiconductor device including an n-channel field effect transistor 10 and a p-channel field effect transistor 30, a stress control film 19 covering a gate electrode 15 of the n-channel field effect transistor 10 undergoes film stress mainly composed of tensile stress. A stress control film 39 covering a gate electrode 15 of the p-channel field effect transistor 30 undergoes film stress mainly caused by compression stress compared to the film 19 of the n-channel field effect transistor 10. Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.
摘要翻译：本发明提供一种包括n沟道场效应晶体管和p沟道场效应晶体管的半导体器件，其全部具有优良的漏极电流特性。在包括n沟道场效应晶体管10和p沟道场效应晶体管30的半导体器件中，覆盖n沟道场效应晶体管10的栅电极15的应力控制膜19经受主要由拉伸应力。与n沟道场效应晶体管10的膜19相比，覆盖p沟道场效应晶体管30的栅电极15的应力控制膜39主要由压缩应力引起的膜应力。因此，预期在n沟道场效应晶体管和p沟道场效应晶体管两者中都会改善漏极电流。因此，通常可以提高特性。

4. 发明申请

US20060214254A1 Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20060214254A1
公开(公告)日：2006-09-28
申请号：US11443226
申请日：2006-05-31
申请人： Norio Ishitsuka , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Masahito Takahashi , Norio Suzuki , Shuji Ikeda , Hideki Tanaka , Hiroyuki Mima
发明人： Norio Ishitsuka , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Masahito Takahashi , Norio Suzuki , Shuji Ikeda , Hideki Tanaka , Hiroyuki Mima
IPC分类号： H01L29/00
CPC分类号： H01L27/11526 , H01L21/28123 , H01L21/76224 , H01L21/823481 , H01L27/105 , H01L27/11546
摘要： To suppress occurrence of defects in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.
摘要翻译：为了抑制半导体衬底中的缺陷的发生，半导体器件通过具有：半导体衬底; 具有形成在所述半导体衬底中的沟槽的元件隔离区域和嵌入所述沟槽中的嵌入绝缘膜; 形成在元件隔离区域附近形成的有源区，其中形成栅极绝缘膜并在栅极绝缘膜上形成栅电极; 以及形成为使得栅电极的至少一部分位于元件隔离区域上的区域，以及在栅电极为第一元件隔离区域的嵌入绝缘膜的上侧的第一边缘表面定位在位于绝缘膜的第二边缘表面上方的第二元件隔离区域中，栅极电极膜未被定位。

5. 发明授权

US07084477B2 Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07084477B2
公开(公告)日：2006-08-01
申请号：US10600771
申请日：2003-06-23
申请人： Norio Ishitsuka , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Masahito Takahashi , Norio Suzuki , Shuji Ikeda , Hideki Tanaka , Hiroyuki Mima
发明人： Norio Ishitsuka , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Masahito Takahashi , Norio Suzuki , Shuji Ikeda , Hideki Tanaka , Hiroyuki Mima
IPC分类号： H01L29/00
CPC分类号： H01L27/11526 , H01L21/28123 , H01L21/76224 , H01L21/823481 , H01L27/105 , H01L27/11546
摘要： To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.
摘要翻译：为了抑制在半导体衬底中发生的缺陷，半导体器件通过具有：半导体衬底; 具有形成在所述半导体衬底中的沟槽的元件隔离区域和嵌入所述沟槽中的嵌入绝缘膜; 形成在元件隔离区域附近形成的有源区，其中形成栅极绝缘膜并在栅极绝缘膜上形成栅电极; 以及形成为使得栅电极的至少一部分位于元件隔离区域上的区域，以及在栅电极为第一元件隔离区域的嵌入绝缘膜的上侧的第一边缘表面定位在位于绝缘膜的第二边缘表面上方的第二元件隔离区域中，栅极电极膜未被定位。

6. 发明申请

US20050196935A1 Semiconductor device and process for producing the same 有权
公开(公告)号：US20050196935A1
公开(公告)日：2005-09-08
申请号：US11108827
申请日：2005-04-19
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
IPC分类号： H01L21/31 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76232 , H01L21/76235 , H01L29/78
摘要： A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

7. 发明授权

US06881646B2 Semiconductor device and process for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06881646B2
公开(公告)日：2005-04-19
申请号：US10392916
申请日：2003-03-21
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Norio Suzuki , Yasushi Matsuda , Yasuko Yoshida , Hirohiko Yamamoto , Masamichi Kobayashi , Akira Takamatsu , Hirofumi Shimizu , Kazushi Fukuda , Shinichi Horibe , Toshio Nozoe
IPC分类号： H01L21/31 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76232 , H01L21/76235 , H01L29/78
摘要： A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
摘要翻译：一种制造半导体器件的方法，该半导体器件具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤。通过减小半导体衬底上的元件隔离槽的槽上边缘周围的应力产生，从而优化元件隔离槽的形状并使器件更精细并提高器件电气特性来制造器件。

8. 发明授权

US06348396B1 Semiconductor device and production thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：US06348396B1
公开(公告)日：2002-02-19
申请号：US09702786
申请日：2000-11-01
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A semiconductor device having a SGI structure produced by selecting D, T and R values for satisfying the formula: D
摘要翻译：具有SGI结构的半导体器件通过选择满足下式的D，T和R值产生：其中D是元件形成区域的宽度，T是以微米为单位的槽的热氧化量，R是在槽的端部底部的曲率半径具有优异的性能，例如在硅衬底中的凹槽底部产生的应力减小，并且不产生异常结漏电流。

9. 发明授权

US6090684A Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US6090684A
公开(公告)日：2000-07-18
申请号：US363184
申请日：1999-07-29
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
IPC分类号： H01L21/76 , H01L21/762 , H01L29/78
CPC分类号： H01L21/76232 , Y10S148/05
摘要： A shallow groove isolation structure (SGI) electrically insulates adjoining transistors on a semiconductor substrate. A pad oxide film is formed on the semiconductor substrate and an oxidation inhibition film is formed on the pad oxide film. Parts of the oxide inhibition film and pad oxide film are removed to form the groove. In particular, the pad oxide film is removed from an upper edge of the groove within a range of 5 to 40 nm. A region of the groove is oxidized in an oxidation environment with a cast ratio of hydrogen (H.sub.2) to oxygen (O.sub.2) being less than or equal to 0.5. At this ratio, the oxidizing progresses under low stress at the upper groove edges of the substrate thereby enabling rounding of the upper groove edges without creating a level difference at or near the upper groove edge on the substrate surface.
摘要翻译：浅沟隔离结构（SGI）使半导体衬底上的相邻晶体管电绝缘。在半导体基板上形成衬垫氧化膜，在衬垫氧化膜上形成氧化抑制膜。除去氧化物抑制膜和垫氧化膜的一部分以形成槽。特别地，在5〜40nm的范围内，从槽的上边缘去除衬垫氧化膜。凹槽的区域在氢（H 2）与氧（O 2）的铸造比小于或等于0.5的氧化环境中被氧化。在该比例下，在基板的上槽边缘处的低应力下氧化进行，从而能够在上槽边缘的四舍五入，而不会在基板表面上的上槽边缘处或附近产生水平差。

10. 发明授权

US06403446B1 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06403446B1
公开(公告)日：2002-06-11
申请号：US09536447
申请日：2000-03-28
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , Y10S148/05
摘要： Manufacturing a semiconductor device avoiding an increase of transistor leak current or reduction of the withstanding voltage characteristics is by at least one of: The pad oxide film is removed along the substrate surface from the upper edge of the groove over a distance ranging from 5 to 40 nm: The exposed surface of the semiconductor substrate undergoes removal by isotropic etching within 20 nm; and oxidizing a groove portion formed in a semiconductor substrate in an oxidation environment with a gas ratio of hydrogen (H2) to oxygen (O2) being less than or equal to 0.5, an increase of the curvature radius beyond 3nm is achieved without associating the risk of creation of any level difference on the substrate surface at or near the upper groove edge portions in a groove separation structure. This eliminates either an increase of transistor leak current or reduction of the withstanding voltage characteristics thereof otherwise occurring due to local electric field concentration near or around the terminate ends of a gate electrode film which in turn leads to an ability to improve electrical reliability of transistors used.
摘要翻译：制造半导体器件避免晶体管泄漏电流的增加或耐压特性的降低是至少以下之一：衬垫氧化膜沿着衬底表面从沟槽的上边缘移除5至40的距离 nm：通过各向同性蚀刻在20nm内去除半导体衬底的暴露表面; 并且在氧（H2）与氧气（O2）的气体比小于或等于0.5的氧化环境中氧化形成在半导体衬底中的沟槽部分，实现曲率半径超过3nm的增加，而不会使风险在槽分离结构中的上槽边缘部分处或附近在基板表面上产生任何水平差。这消除了晶体管泄漏电流的增加或由于栅极电极膜的端部附近或周围的局部电场浓度而导致的耐压特性的降低，这进而导致提高使用的晶体管的电可靠性的能力。

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