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1. 发明授权

US07916561B2 DLL circuit, imaging device, and memory device 有权
标题翻译： DLL电路，成像设备和存储器件
公开(公告)号：US07916561B2
公开(公告)日：2011-03-29
申请号：US12332844
申请日：2008-12-11
申请人： Norihide Kinugasa , Mitsuhiko Otani , Naohisa Hatani , Takayasu Kitou
发明人： Norihide Kinugasa , Mitsuhiko Otani , Naohisa Hatani , Takayasu Kitou
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , H03D13/004 , H03L7/0812 , H03L7/0891
摘要： A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.
摘要翻译：可变延迟电路连续地延迟输入时钟以产生具有不同相位的多个延迟时钟。相位比较电路接收作为延迟时钟或输入时钟之一的第一参考时钟和作为延迟时钟之一并且其相位滞后于第一参考时钟之一的第二参考时钟，指定一个并且根据第一参考时钟和第二参考时钟的电压电平仅在验证间隔期间比较第一和第二参考时钟的相位。延迟控制电路根据由相位比较电路获得的比较结果控制可变延迟电路中的延迟时间。

2. 发明申请

US20090154268A1 DLL CIRCUIT, IMAGING DEVICE, AND MEMORY DEVICE 有权
标题翻译： DLL电路，成像设备和存储器件
公开(公告)号：US20090154268A1
公开(公告)日：2009-06-18
申请号：US12332844
申请日：2008-12-11
申请人： Norihide KINUGASA , Mitsuhiko Otani , Naohisa Hatani , Takayasu Kitou
发明人： Norihide KINUGASA , Mitsuhiko Otani , Naohisa Hatani , Takayasu Kitou
IPC分类号： H03L7/06 , G11C7/00 , H03D3/24
CPC分类号： G11C7/22 , G11C7/222 , H03D13/004 , H03L7/0812 , H03L7/0891
摘要： A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.
摘要翻译：可变延迟电路连续地延迟输入时钟以产生具有不同相位的多个延迟时钟。相位比较电路接收作为延迟时钟或输入时钟之一的第一参考时钟和作为延迟时钟之一并且其相位滞后于第一参考时钟之一的第二参考时钟，指定一个并且根据第一参考时钟和第二参考时钟的电压电平仅在验证间隔期间比较第一和第二参考时钟的相位。延迟控制电路根据由相位比较电路获得的比较结果控制可变延迟电路中的延迟时间。

3. 发明申请

US20070008282A1 Pipeline A/D converter and method of pipeline A/D conversion 有权
标题翻译：管道A / D转换器和管道A / D转换方法
公开(公告)号：US20070008282A1
公开(公告)日：2007-01-11
申请号：US11479011
申请日：2006-06-30
申请人： Shinichi Ogita , Mitsuhiko Otani , Kouji Yamaguchi , Takayasu Kito , Naohisa Hatani
发明人： Shinichi Ogita , Mitsuhiko Otani , Kouji Yamaguchi , Takayasu Kito , Naohisa Hatani
IPC分类号： G09G5/08
CPC分类号： H03M1/108 , H03M1/442
摘要： A pipeline A/D converter of the present invention includes a plurality of stages each operating for A/D conversion and a digital computing portion that outputs an A/D converted signal based on a digital signal output from each of the stages. In each of the stages, an analog signal from the preceding stage is sampled by passive elements C1 and C2 in a first period, and one of the passive elements is used as a feedback element in a second period to perform adding/subtracting with respect to the signal sampled by the other passive element. By the control from the digital computing portion, a test signal Tink is used instead of an analog output signal Vo(k−1), and a unique conversion-error value is detected and corrected based on the digital signal obtained by the operation of each of the stages. It is possible to obtain a high-resolution A/D convert that can suppress a conversion error caused by the relative error of capacitors used for analog signal processing without decreasing the speed of A/D conversion.
摘要翻译：本发明的流水线A / D转换器包括多个用于A / D转换的工作级和基于从每个级输出的数字信号输出A / D转换的信号的数字计算部分。在每个阶段中，来自前一级的模拟信号在第一周期中被无源元件C 1和C 2采样，并且在第二周期中将无源元件中的一个作为反馈元件用于执行与/ 相对于被另一无源元件采样的信号。通过数字计算部分的控制，使用测试信号Tink而不是模拟输出信号Vo（k-1），并且基于通过每个操作获得的数字信号来检测和校正唯一的转换误差值的阶段。可以获得可以抑制由模拟信号处理所使用的电容器的相对误差引起的转换误差而不降低A / D转换速度的高分辨率A / D转换。

4. 发明申请

US20060232314A1 Phase adjustment device, phase adjustment method, and semiconductor integrated circuit 审中-公开
标题翻译：相位调整装置，相位调整方法和半导体集成电路
公开(公告)号：US20060232314A1
公开(公告)日：2006-10-19
申请号：US11396453
申请日：2006-04-04
申请人： Naohisa Hatani , Mitsuhiko Otani , Shinichi Ogita , Kouji Yamaguti , Takayasu Kito
发明人： Naohisa Hatani , Mitsuhiko Otani , Shinichi Ogita , Kouji Yamaguti , Takayasu Kito
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03K2005/00058 , H03L7/07 , H03L7/0814
摘要： A phase adjustment device which adjusts a phase difference between a first output pulse signal and a second output pulse signal according to a phase difference between a first input pulse signal and a second input pulse signal, the phase adjustment device including: a first selection unit which selects one of the first input pulse signal and an adjustment pulse signal that is used for adjustment; a second selection unit which selects one of the second input pulse signal and the adjustment pulse signal; a first delay unit which delays the signal selected by the second selection unit, and a delay amount of the first delay unit is adjustable; a first output unit which outputs, as the first output pulse signal, the signal selected by the first selection unit; a second output unit which outputs, as the second output pulse signal, the signal delayed by the first delay unit; and a phase adjustment unit which adjusts the delay amount so as to equalize phases of the first output pulse signal and the second output pulse signal, in the case where both the first selection unit and the second selection unit have selected the adjustment pulse signal.
摘要翻译：一种相位调整装置，其根据第一输入脉冲信号和第二输入脉冲信号之间的相位差来调整第一输出脉冲信号和第二输出脉冲信号之间的相位差，所述相位调整装置包括：第一选择单元，选择第一输入脉冲信号和用于调整的调整脉冲信号之一; 第二选择单元，其选择第二输入脉冲信号和调整脉冲信号中的一个; 第一延迟单元，其延迟由第二选择单元选择的信号，并且第一延迟单元的延迟量是可调节的; 第一输出单元，其输出由第一选择单元选择的信号作为第一输出脉冲信号; 输出由第一延迟单元延迟的信号作为第二输出脉冲信号的第二输出单元; 以及在所述第一选择单元和所述第二选择单元都选择了所述调整脉冲信号的情况下，调整所述延迟量以均衡所述第一输出脉冲信号和所述第二输出脉冲信号的相位的相位调整单元。

5. 发明申请

US20080170086A1 FRONT END SIGNAL PROCESSING METHOD AND FRONT END SIGNAL PROCESSOR 审中-公开
标题翻译：前端信号处理方法和前端信号处理器
公开(公告)号：US20080170086A1
公开(公告)日：2008-07-17
申请号：US11971865
申请日：2008-01-09
申请人： Naohisa Hatani , Mitsuhiko Otani , Kouji Yamaguchi , Shinichi Ogita
发明人： Naohisa Hatani , Mitsuhiko Otani , Kouji Yamaguchi , Shinichi Ogita
IPC分类号： G09G5/10
CPC分类号： H04N5/361
摘要： (a) The luminance levels of the optical black part pixels included in the output signal of an image sensor are detected and digitized, (b) the digitized luminance levels of the optical black part pixels are averaged, (c) the number of pixels on which averaging is performed is counted, (d) a control signal is generated when the count value of the number of pixels reaches a predetermined value, (e) the black level of the output signal of the image sensor is determined from the averaged luminance level in response to the control signal, and (f) the luminance levels of the effective part pixels included in the output signal of the image sensor whose black level is determined are detected and digitized.
摘要翻译：（a）检测并数字化包括在图像传感器的输出信号中的光学黑色部分像素的亮度级，（b）光学黑色部分像素的数字化亮度级别被平均化，（c）计算平均值，（d）当像素数量的计数值达到预定值时产生控制信号，（e）从平均亮度级确定图像传感器的输出信号的黑电平响应于控制信号，并且（f）检测并数字化确定了黑电平的图像传感器的输出信号中包括的有效部分像素的亮度级。

6. 发明申请

US20070216778A1 Front-end signal processing circuit and imaging device 失效
标题翻译：前端信号处理电路及成像装置
公开(公告)号：US20070216778A1
公开(公告)日：2007-09-20
申请号：US11723117
申请日：2007-03-16
申请人： Naohisa Hatani , Mitsuhiko Otani , Kouji Yamaguchi
发明人： Naohisa Hatani , Mitsuhiko Otani , Kouji Yamaguchi
IPC分类号： H04N5/228
CPC分类号： H04N5/361 , H04N5/3575 , H04N5/3655
摘要： A front-end signal processing circuit that stabilizes a black level of an output signal of an image sensor in a prescribed set level, without being influenced by a DC offset component of circuit elements making up a feedback loop, and an imaging device including such the front-end signal processing circuit, are provided. The front-end signal processing circuit includes a feedback loop made up of a luminance detecting/digitizing section and a black level clamp section, and clamps a black level of an output signal of an image sensor to a prescribed set level. The front-end signal processing circuit further includes an offset correction section. The offset correction section stores an offset value being a difference between a signal level of an OB region of the image sensor and the prescribed level, subtracts the offset value from a digital luminance signal corresponding to an effective pixel region of the image sensor, and outputs the obtained signal.
摘要翻译：一种前端信号处理电路，其在规定的设定电平下稳定图像传感器的输出信号的黑电平，而不受构成反馈回路的电路元件的DC偏移分量的影响;以及成像装置，前端信号处理电路。前端信号处理电路包括由亮度检测/数字化部分和黑电平钳位部分构成的反馈回路，并将图像传感器的输出信号的黑电平钳位到规定的设定电平。前端信号处理电路还包括偏移校正部分。偏移校正部存储作为图像传感器的OB区域的信号电平与规定电平之间的差的偏移值，从与图像传感器的有效像素区域对应的数字亮度信号中减去偏移值，并输出获得的信号。

7. 发明授权

US07652690B2 Front-end signal processing circuit and imaging device 失效
标题翻译：前端信号处理电路及成像装置
公开(公告)号：US07652690B2
公开(公告)日：2010-01-26
申请号：US11723117
申请日：2007-03-16
申请人： Naohisa Hatani , Mitsuhiko Otani , Kouji Yamaguchi
发明人： Naohisa Hatani , Mitsuhiko Otani , Kouji Yamaguchi
IPC分类号： H04N5/228
CPC分类号： H04N5/361 , H04N5/3575 , H04N5/3655
摘要： A front-end signal processing circuit that stabilizes a black level of an output signal of an image sensor in a prescribed set level, without being influenced by a DC offset component of circuit elements making up a feedback loop, and an imaging device including such the front-end signal processing circuit, are provided.The front-end signal processing circuit includes a feedback loop made up of a luminance detecting/digitizing section and a black level clamp section, and clamps a black level of an output signal of an image sensor to a prescribed set level. The front-end signal processing circuit further includes an offset correction section. The offset correction section stores an offset value being a difference between a signal level of an OB region of the image sensor and the prescribed level, subtracts the offset value from a digital luminance signal corresponding to an effective pixel region of the image sensor, and outputs the obtained signal.
摘要翻译：一种前端信号处理电路，其在规定的设定电平下稳定图像传感器的输出信号的黑电平，而不受构成反馈回路的电路元件的DC偏移分量的影响;以及成像装置，前端信号处理电路。前端信号处理电路包括由亮度检测/数字化部分和黑电平钳位部分构成的反馈回路，并将图像传感器的输出信号的黑电平钳位到规定的设定电平。前端信号处理电路还包括偏移校正部分。偏移校正部存储作为图像传感器的OB区域的信号电平与规定电平之间的差的偏移值，从与图像传感器的有效像素区域对应的数字亮度信号中减去偏移值，并输出获得的信号。

8. 发明授权

US07348916B2 Pipeline A/D converter and method of pipeline A/D conversion 有权
标题翻译：管道A / D转换器和管道A / D转换方法
公开(公告)号：US07348916B2
公开(公告)日：2008-03-25
申请号：US11479011
申请日：2006-06-30
申请人： Shinichi Ogita , Mitsuhiko Otani , Kouji Yamaguchi , Takayasu Kito , Naohisa Hatani
发明人： Shinichi Ogita , Mitsuhiko Otani , Kouji Yamaguchi , Takayasu Kito , Naohisa Hatani
IPC分类号： H03M1/38
CPC分类号： H03M1/108 , H03M1/442
摘要： A pipeline A/D converter of the present invention includes a plurality of stages each operating for A/D conversion and a digital computing portion that outputs an A/D converted signal based on a digital signal output from each of the stages. In each of the stages, an analog signal from the preceding stage is sampled by passive elements C1 and C2 in a first period, and one of the passive elements is used as a feedback element in a second period to perform adding/subtracting with respect to the signal sampled by the other passive element. By the control from the digital computing portion, a test signal Tink is used instead of an analog output signal Vo(k−1), and a unique conversion-error value is detected and corrected based on the digital signal obtained by the operation of each of the stages. It is possible to obtain a high-resolution A/D convert that can suppress a conversion error caused by the relative error of capacitors used for analog signal processing without decreasing the speed of A/D conversion.
摘要翻译：本发明的流水线A / D转换器包括多个用于A / D转换的工作级和基于从每个级输出的数字信号输出A / D转换的信号的数字计算部分。在每个阶段中，来自前一级的模拟信号在第一周期中被无源元件C 1和C 2采样，并且在第二周期中将无源元件中的一个作为反馈元件用于执行与/ 相对于被另一无源元件采样的信号。通过数字计算部分的控制，使用测试信号Tink而不是模拟输出信号Vo（k-1），并且基于通过每个操作获得的数字信号来检测和校正唯一的转换误差值的阶段。可以获得可以抑制由模拟信号处理所使用的电容器的相对误差引起的转换误差而不降低A / D转换速度的高分辨率A / D转换。

9. 发明申请

US20060170805A1 CCD solid-state image pick-up device, analog signal processing system and analog signal processing method 审中-公开
标题翻译： CCD固态摄像装置，模拟信号处理系统和模拟信号处理方法
公开(公告)号：US20060170805A1
公开(公告)日：2006-08-03
申请号：US11342653
申请日：2006-01-31
申请人： Takayasu Kito , Shinichi Ogita , Kouji Yamaguchi , Naohisa Hatani , Keijirou Itakura , Mitsuhiko Otani , Yasumasa Yoshikawa
发明人： Takayasu Kito , Shinichi Ogita , Kouji Yamaguchi , Naohisa Hatani , Keijirou Itakura , Mitsuhiko Otani , Yasumasa Yoshikawa
IPC分类号： H04N5/335
CPC分类号： H04N5/361 , H04N5/372 , H04N5/378
摘要： In a CCD solid-state image pick-up device according to the present invention, a solid-state image pick-up circuit formed by a sensor part, a horizontal transfer register part and a floating diffusion amplifier converts a photo signal into a voltage signal and outputs the voltage signal, and a voltage-current conversion circuit converts the voltage signal output from the solid-state image pick-up circuit into a current signal. A current-driven black signal component detect/remove circuit then removes a black signal component from the current signal output from the CCD solid-state image pick-up device, and an image signal component alone is output as a current image signal. A current-voltage conversion circuit converts the current image signal into a voltage image signal.
摘要翻译：在根据本发明的CCD固态摄像装置中，由传感器部分，水平传送寄存器部分和浮动扩散放大器形成的固态图像拾取电路将光信号转换成电压信号并输出电压信号，电压 - 电流转换电路将从固态摄像电路输出的电压信号转换为电流信号。电流驱动的黑色信号分量检测/去除电路然后从CCD固态图像拾取装置输出的当前信号中除去黑色信号分量，并且仅将图像信号分量作为当前图像信号输出。电流 - 电压转换电路将当前图像信号转换为电压图像信号。

10. 发明授权

US5841389A Two-step parallel A/D converter 失效
标题翻译：两级并行A / D转换器
公开(公告)号：US5841389A
公开(公告)日：1998-11-24
申请号：US833965
申请日：1997-04-11
申请人： Norihide Kinugasa , Mitsuhiko Otani , Katsumi Hironaka , Shinichi Ogita
发明人： Norihide Kinugasa , Mitsuhiko Otani , Katsumi Hironaka , Shinichi Ogita
IPC分类号： H03M1/16 , H03M1/36
CPC分类号： H03M1/165 , H03M1/365
摘要： Provided is a two-step parallel A/D converter capable of operating at a higher speed than in the prior art and easily performing correction of upper bit data. An upper limit voltage V.sub.H of a voltage range for lower bit conversion is amplified on the basis of a median voltage V.sub.M of the voltage range by a second differential amplifier, and the amplified voltage is set to a high level reference voltage SUB.sub.H for lower bit conversion. A lower limit voltage V.sub.L of the voltage range is amplified on the basis of the median voltage V.sub.M by a third differential amplifier, and the amplified voltage is set to a low level reference voltage SUB.sub.L for lower bit conversion. A voltage V.sub.IN of an input analog signal is amplified on the basis of the voltage V.sub.M by a first differential amplifier, and lower bit data is obtained from a position between the voltage SUB.sub.H and the voltage SUB.sub.L which is occupied by an obtained voltage SUB.sub.IN. The voltages SUB.sub.H and SUB.sub.L are not changed by the voltage V.sub.IN of the input analog signal. Consequently, a settling time can be shortened more than in the prior art.
摘要翻译：提供了一种两级并行A / D转换器，其能够以比现有技术更高的速度运行并且容易地执行高位数据的校正。基于第二差分放大器的电压范围的中值电压VM来放大用于低位转换的电压范围的上限电压VH，并且将放大的电压设置为用于较低位转换的高电平参考电压SUBH 。电压范围的下限电压VL由第三差分放大器基于中值电压VM放大，放大电压被设定为低电平基准电压SUBL用于低位转换。输入模拟信号的电压VIN通过第一差分放大器基于电压VM放大，并且从电压SUBH和所获得的电压SUBIN占据的电压SUBL之间的位置获得低位数据。电压SUBH和SUBL不会被输入模拟信号的电压VIN改变。因此，与现有技术相比，可以缩短建立时间。

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