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1. 发明申请

US20090154268A1 DLL CIRCUIT, IMAGING DEVICE, AND MEMORY DEVICE 有权
标题翻译： DLL电路，成像设备和存储器件
公开(公告)号：US20090154268A1
公开(公告)日：2009-06-18
申请号：US12332844
申请日：2008-12-11
申请人： Norihide KINUGASA , Mitsuhiko Otani , Naohisa Hatani , Takayasu Kitou
发明人： Norihide KINUGASA , Mitsuhiko Otani , Naohisa Hatani , Takayasu Kitou
IPC分类号： H03L7/06 , G11C7/00 , H03D3/24
CPC分类号： G11C7/22 , G11C7/222 , H03D13/004 , H03L7/0812 , H03L7/0891
摘要： A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.
摘要翻译：可变延迟电路连续地延迟输入时钟以产生具有不同相位的多个延迟时钟。相位比较电路接收作为延迟时钟或输入时钟之一的第一参考时钟和作为延迟时钟之一并且其相位滞后于第一参考时钟之一的第二参考时钟，指定一个并且根据第一参考时钟和第二参考时钟的电压电平仅在验证间隔期间比较第一和第二参考时钟的相位。延迟控制电路根据由相位比较电路获得的比较结果控制可变延迟电路中的延迟时间。

2. 发明申请

US20080111920A1 VERTICAL FREQUENCY DISTINCTION CIRCUIT, VIDEO DISPLAY APPARATUS, AND VERTICAL FREQUENCY DISTINCTION METHOD 审中-公开
标题翻译：垂直频率分辨电路，视频显示设备和垂直频率分辨方法
公开(公告)号：US20080111920A1
公开(公告)日：2008-05-15
申请号：US11874387
申请日：2007-10-18
申请人： Sachi OTA , Norihide KINUGASA
发明人： Sachi OTA , Norihide KINUGASA
IPC分类号： H03L7/00 , H04N5/94
CPC分类号： H04N5/46 , H04N5/04 , H04N5/21 , H04N9/642
摘要： There is provided a vertical frequency distinction circuit and a vertical frequency distinction method capable of reducing a chip area, and a video display apparatus having the vertical frequency distinction circuit. A vertical control pulse generating section of the vertical frequency distinction circuit generates a noise eliminating signal for disabling input of noise during a predetermined period until arrival of a vertical synchronization signal. A distinction result latch section samples the noise eliminating signal and an inversion signal of the noise eliminating signal at the timing of input of the vertical synchronization signal, to generate two output signals. An output selecting section selects either one of the two output signals of the distinction result latch section based on a mode setting signal, to output the selected signal as a distinction result signal.
摘要翻译：提供了能够减少芯片面积的垂直频率区分电路和垂直频率区别方法，以及具有垂直频率区分电路的视频显示装置。垂直频率区分电路的垂直控制脉冲产生部分产生一个噪声消除信号，用于在直到垂直同步信号到达之前的预定时段内禁止输入噪声。区分结果锁存部分在垂直同步信号的输入定时对噪声消除信号和噪声消除信号的反相信号进行采样，以产生两个输出信号。输出选择部分基于模式设置信号选择区分结果锁存部分的两个输出信号中的一个，以输出所选择的信号作为区分结果信号。

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