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    • 2. 发明授权
    • Method of manufacturing insulated gate semiconductor device
    • 绝缘栅半导体器件的制造方法
    • US07125787B2
    • 2006-10-24
    • US10720378
    • 2003-11-25
    • Nobuyuki SekikawaMasaaki MomenWataru AndohKoichi Hirata
    • Nobuyuki SekikawaMasaaki MomenWataru AndohKoichi Hirata
    • H01L21/3205H01L21/4763H01L29/76
    • H01L29/66575H01L29/42368H01L29/7834
    • A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t2 of the gate electrode 10 on the second gate oxide films 6A and 6B is thinner than the thickness t1 of the prior art. Therefore, the height gap h2 between the gate electrode 10 and the N+type source layer 11 and the height gap h2 between the gate electrode 10 and the N+type drain layer 12 become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film 13.
    • 栅电极包括残留在第一氧化膜上的第一多晶硅膜,叠加在多晶硅层上的第二多晶硅层8的一部分,以及部分地延伸在第二栅极氧化物膜上的第二多晶硅层的一部分。 因此,第一栅极氧化膜上的栅电极的厚度与现有技术的栅电极的厚度相同,但是第二栅极氧化膜6A和6B上的栅电极10的膜厚度t 2 比现有技术的厚度t 1薄。 因此,与现有技术相比,栅电极10和N +型源极层11之间的高度间隙h 2和栅电极10与N +型漏极层12之间的高度间隙h 2变小, 层间氧化膜13的平坦度提高。
    • 3. 发明授权
    • Insulated gate semiconductor device and its manufacturing method
    • 绝缘栅半导体器件及其制造方法
    • US06690070B2
    • 2004-02-10
    • US09925628
    • 2001-08-10
    • Nobuyuki SekikawaMasaaki MomenWataru AndohKoichi Hirata
    • Nobuyuki SekikawaMasaaki MomenWataru AndohKoichi Hirata
    • H01L31119
    • H01L29/66575H01L29/42368H01L29/7834
    • A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t2 of the gate electrode 10 on the second gate oxide films 6A and 6B is thinner than the thickness t1 of the prior art. Therefore, the height gap h2 between the gate electrode 10 and the N + type source layer 11 and the height gap h2 between the gate electrode 10 and the N + type drain layer 12 become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film 13.
    • 栅电极包括残留在第一氧化膜上的第一多晶硅膜,叠加在多晶硅层上的第二多晶硅层8的一部分,以及部分地延伸在第二栅极氧化物膜上的第二多晶硅层的一部分。 因此,第一栅极氧化膜上的栅电极的厚度与现有技术的栅电极的厚度相同,但是第二栅极氧化膜6A和6B上的栅电极10的膜厚度t2比 现有技术的厚度t1。 因此,与现有技术相比,栅电极10和N +型源极层11之间的高度间隙h2和栅电极10与N +型漏层12之间的高度间隙h2变小 层间氧化膜13的平坦度。