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1. 发明申请

US20140021003A1 ELECTROMAGNETIC CLUTCH 有权
标题翻译：电磁离合器
公开(公告)号：US20140021003A1
公开(公告)日：2014-01-23
申请号：US14008382
申请日：2012-04-02
申请人： Ryutaro Nakano , Nobuyuki Sekikawa , Hiromi Okubayashi
发明人： Ryutaro Nakano , Nobuyuki Sekikawa , Hiromi Okubayashi
IPC分类号： F16D27/14
CPC分类号： F16D27/14 , F16D27/06 , F16D27/112 , F16D2027/008
摘要： The electromagnetic clutch (X) includes a rotating shaft (1): a magnetic pole body (2) and a rotor (3) disposed to face each other along an axial direction of the rotating shaft (1); and an armature (4) capable of moving in a direction attachable to or detachable from the rotor (3) along the axial direction of the rotating shaft and Ruining a magnetic circuit with the magnetic pole body and the rotor. The armature is moved in the axial direction of the rotating shaft by electromagnetic suction force to press the rotor when an exciting coil (21) is in an excitation state. The rotating shaft is configured by an input side shaft portion (11) which is a non-magnetic body and formed of a material having enough strength to support rotation of the rotor and the armature; and an output side shaft portion (12) which is a magnetic body.
摘要翻译：电磁离合器（X）包括沿着旋转轴（1）的轴向彼此相对设置的旋转轴（1），磁极体（2）和转子（3）。以及电枢（4），其能够沿着与所述转子（3）的轴向相连接或可从所述转子（3）拆卸的方向移动，并且与所述磁极体和所述转子断开磁路。当励磁线圈（21）处于激励状态时，电枢通过电磁抽吸力在旋转轴的轴向上移动以按压转子。旋转轴由作为非磁性体的输入侧轴部（11）构成，由具有足够强度的材料形成，以支撑转子和电枢的旋转; 和作为磁性体的输出侧轴部（12）。

2. 发明授权

US07125787B2 Method of manufacturing insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件的制造方法
公开(公告)号：US07125787B2
公开(公告)日：2006-10-24
申请号：US10720378
申请日：2003-11-25
申请人： Nobuyuki Sekikawa , Masaaki Momen , Wataru Andoh , Koichi Hirata
发明人： Nobuyuki Sekikawa , Masaaki Momen , Wataru Andoh , Koichi Hirata
IPC分类号： H01L21/3205 , H01L21/4763 , H01L29/76
CPC分类号： H01L29/66575 , H01L29/42368 , H01L29/7834
摘要： A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t2 of the gate electrode 10 on the second gate oxide films 6A and 6B is thinner than the thickness t1 of the prior art. Therefore, the height gap h2 between the gate electrode 10 and the N+type source layer 11 and the height gap h2 between the gate electrode 10 and the N+type drain layer 12 become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film 13.
摘要翻译：栅电极包括残留在第一氧化膜上的第一多晶硅膜，叠加在多晶硅层上的第二多晶硅层8的一部分，以及部分地延伸在第二栅极氧化物膜上的第二多晶硅层的一部分。因此，第一栅极氧化膜上的栅电极的厚度与现有技术的栅电极的厚度相同，但是第二栅极氧化膜6A和6B上的栅电极10的膜厚度t 2 比现有技术的厚度t 1薄。因此，与现有技术相比，栅电极10和N +型源极层11之间的高度间隙h 2和栅电极10与N +型漏极层12之间的高度间隙h 2变小，层间氧化膜13的平坦度提高。

3. 发明授权

US5141881A Method for manufacturing a semiconductor integrated circuit 失效
标题翻译：制造半导体集成电路的方法
公开(公告)号：US5141881A
公开(公告)日：1992-08-25
申请号：US510469
申请日：1990-04-18
申请人： Kazuo Takeda , Toshimasa Sadakata , Teruo Tabata , Nobuyuki Sekikawa , Tadayoshi Takada , Yasuhiro Tamada , Yoshiaki Sano
发明人： Kazuo Takeda , Toshimasa Sadakata , Teruo Tabata , Nobuyuki Sekikawa , Tadayoshi Takada , Yasuhiro Tamada , Yoshiaki Sano
IPC分类号： H01L21/761 , H01L21/8222
CPC分类号： H01L21/761 , H01L21/8222 , Y10S148/009 , Y10S148/01
摘要： A method of making a semiconductor integrated circuit provided with an isolating region constituted of an upper and lower isolating regions, and integrated circuit element regions is disclosed, wherein: the lower isolating region is diffused upward to a depth of a little more than half the thickness of an epitaxial layer to link with the upper isolating region prior to a doping of the upper isolating region; the doping of the lower isolating region and integrated circuit element regions, is implemented by means of ion implantation through a resist film which is capable of blocking ions implanted and in which specified doping windows have been formed in advance, and a SiO.sub.2 film is used as a reference mask in an ion implanting step, and the respective borders of the upper isolating region and the specified regions of the circuit elements is determined by self-alignment. The method has advantages that the upper isolating region can be prepared by heat-treatment for relatively short time, reducing lateral diffusion and the occupied area thereof, and slippage by masking is remarkably reduced, providing a semiconductor integrated circuit with high density.

4. 发明授权

US06693341B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06693341B2
公开(公告)日：2004-02-17
申请号：US10290126
申请日：2002-11-07
申请人： Nobuyuki Sekikawa , Wataru Andoh , Masaaki Anezaki , Masaaki Momen
发明人： Nobuyuki Sekikawa , Wataru Andoh , Masaaki Anezaki , Masaaki Momen
IPC分类号： H01L2900
CPC分类号： H01L21/76202 , H01L21/28052 , H01L21/28123
摘要： When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.
摘要翻译：当通过LOCOS技术形成元件隔离膜时，作为抗氧化膜的底层缓冲层，使用焊盘氧化膜和焊盘多晶硅膜。当形成元件时，它们被用作栅极氧化膜和栅电极的一部分，以松弛元件隔离膜上的栅电极和布线之间的电平差。蚀刻第一多晶硅膜（焊盘多晶硅膜）以留下其一定厚度，以更大程度地放松电平差。在这样的处理中，在使用LOCOS技术的半导体集成电路的制造中，可以减少制造步骤的数量，并且可以缓和栅极绝缘膜上的栅电极与元件隔离膜上的配线之间的电平差。

5. 发明授权

US5193278A Rotary cutter 失效
标题翻译：旋转刀
公开(公告)号：US5193278A
公开(公告)日：1993-03-16
申请号：US863690
申请日：1992-04-02
申请人： Mitsuo Osakabe , Minoru Shibasaki , Toshimichi Kaneniwa , Nobuyuki Sekikawa
发明人： Mitsuo Osakabe , Minoru Shibasaki , Toshimichi Kaneniwa , Nobuyuki Sekikawa
IPC分类号： A01D34/73 , A01D34/416
CPC分类号： A01D34/4162
摘要： Apparatus for cutting foliage having a rotating head and an annular ring mounted for independent rotation in the head. A cam follower is pivotally mounted in the ring and is guided along a circumferential camming surface formed in the head. The camming surface has spaced apart lobes located adjacent to stops. The free end of a supply line is passed over the cam follower and passed out of the ring to a predetermined cutting length. When the head is rotating at operational speed, the resultant centrifugal force of the follower and the line will hold the follower against the stop. If the line is worn or damaged the holding force is decreased and the follower is released and guided over the stop thus allowing the ring to turn relative to the head until the next stop is encountered. This causes a given amount of line to be played out to replenish the damaged or worn section.
摘要翻译：用于切割具有旋转头和环形环的装置，用于在头部中独立旋转。凸轮随动件枢转地安装在环中并且沿着形成在头部中的周向凸轮表面被引导。凸轮表面具有邻近止挡件的间隔开的凸角。供应管线的自由端通过凸轮从动件并从环中流出到预定的切割长度。当头部以操作速度旋转时，从动件和线的合成离心力将保持随动件停止。如果线被磨损或损坏，则保持力减小并且从动件被释放并被引导到止动器上，从而允许环相对于头部转动，直到遇到下一个停止。这会导致给定数量的线路来补充损坏或磨损的部分。

6. 发明授权

US4898839A Semiconductor integrated circuit and manufacturing method therefor 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US4898839A
公开(公告)日：1990-02-06
申请号：US271746
申请日：1988-11-15
申请人： Chikao Fujinuma , Nobuyuki Sekikawa , Teruo Tabata , Tadayoshi Takada , Yoshiaki Sano , Toshimasa Sadakata
发明人： Chikao Fujinuma , Nobuyuki Sekikawa , Teruo Tabata , Tadayoshi Takada , Yoshiaki Sano , Toshimasa Sadakata
IPC分类号： H01L21/761 , H01L21/8248 , H01L27/06
CPC分类号： H01L21/761 , H01L21/8248 , H01L27/0658 , Y10S148/014
摘要： A method of manufacturing a semiconductor integrated circuit comprises the steps of: forming an epitaxial layer covering a semiconductor substrate and buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; forming a lower electrode region of an MIS type capacitor in one of the islands; forming a base region of a vertical bipolar transistor simultaneously with or independently from the lower electrode in another island; depositing a thin dielectric layer of the MIS type capacitor on a portion of the lower electrode region; thereafter selectively diffusing impurities into the surface layer of the base region so as to form an emitter region of the vertical bipolar transistor; and forming an upper electrode of the MIS type capacitor on the thin dielectric layer.
摘要翻译：一种制造半导体集成电路的方法包括以下步骤：形成覆盖半导体衬底和掩埋层的外延层; 形成将外延层分成多个岛的隔离区; 在其中一个岛中形成MIS型电容器的下电极区域; 在另一岛中与下电极同时或独立地形成垂直双极晶体管的基极区; 在所述下电极区域的一部分上沉积所述MIS型电容器的薄介电层; 然后选择性地将杂质扩散到基极区的表面层中，以形成垂直双极晶体管的发射极区; 以及在所述薄介电层上形成所述MIS型电容器的上电极。

7. 发明授权

US06858489B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US06858489B2
公开(公告)日：2005-02-22
申请号：US10656142
申请日：2003-09-08
申请人： Nobuyuki Sekikawa , Koichi Hirata , Masaaki Momen , Shinya Enomoto
发明人： Nobuyuki Sekikawa , Koichi Hirata , Masaaki Momen , Shinya Enomoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L21/00
CPC分类号： H01L27/0629
摘要： This invention is directed to the reduction of voltage dependence and thus allows easy design of integrated semiconductor circuits. The device is equipped with a P− type resistance layer, in which a first voltage is applied to one end and a second voltage is applied to the other end and which is formed on the surface of an N-well region on the semiconductor substrate, a thin oxide film on the resistance layer, and a resistance bias electrode which includes the silicon layer formed on the thin oxide film. By adjusting the voltage applied to the resistance bias electrode, the voltage dependence of the resistance of the resistance layer is reduced.
摘要翻译：本发明涉及降低电压依赖性，从而允许集成半导体电路的简单设计。该器件配备有P-型电阻层，其中第一电压施加到一端，并且第二电压施加到另一端，并且形成在半导体衬底上的N阱区域的表面上，电阻层上的薄氧化膜，以及包含在薄氧化膜上形成的硅层的电阻偏置电极。通过调整施加到电阻偏置电极的电压，电阻层的电阻的电压依赖性降低。

8. 发明授权

US06670236B2 Semiconductor device having capacitance element and method of producing the same 有权
标题翻译：具有电容元件的半导体器件及其制造方法
公开(公告)号：US06670236B2
公开(公告)日：2003-12-30
申请号：US09924047
申请日：2001-08-07
申请人： Nobuyuki Sekikawa , Koichi Hirata , Wataru Andoh , Noriyasu Katagiri
发明人： Nobuyuki Sekikawa , Koichi Hirata , Wataru Andoh , Noriyasu Katagiri
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L27/1085 , H01L29/94
摘要： To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film (2) and the first polycrystalline silicon layer (3) are used as a stress buffering material at the time of formation of the element separation oxide film. These are not removed and used as the capacitance insulation film and a portion of the upper electrode of the capacitance element. Thereby, the removing process of the pad•polycrystalline silicon layer, and the dummy oxidation and its removing process in the conventional example, can be omitted and the process can be shortened. Further, a problem of the impurity enhanced oxidation at the time of formation of the capacitance insulation film can be solved.
摘要翻译：缩短具有电容元件的半导体器件的制造工序。在形成元件分离氧化膜时，将衬垫氧化膜（2）和第一多晶硅层（3）用作应力缓冲材料。这些不被去除并用作电容绝缘膜和电容元件的上部电极的一部分。由此，可以省略在多个实施例中的多晶硅层的去除处理以及虚拟氧化及其去除工艺，并且可以缩短处理。此外，可以解决在形成电容绝缘膜时杂质增强氧化的问题。

9. 发明授权

US06489661B2 Method of manufacturing semiconductor device and semiconductor device 有权
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US06489661B2
公开(公告)日：2002-12-03
申请号：US09783794
申请日：2001-02-15
申请人： Nobuyuki Sekikawa , Wataru Andoh , Masaaki Anezaki , Masaaki Momen
发明人： Nobuyuki Sekikawa , Wataru Andoh , Masaaki Anezaki , Masaaki Momen
IPC分类号： H01L2900
CPC分类号： H01L21/76202 , H01L21/28052 , H01L21/28123
摘要： When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.
摘要翻译：当通过LOCOS技术形成元件隔离膜时，作为抗氧化膜的底层缓冲层，使用焊盘氧化膜和焊盘多晶硅膜。当形成元件时，它们被用作栅极氧化膜和栅电极的一部分，以松弛元件隔离膜上的栅电极和布线之间的电平差。蚀刻第一多晶硅膜（焊盘多晶硅膜）以留下其一定厚度，以更大程度地放松电平差。在这样的处理中，在使用LOCOS技术的半导体集成电路的制造中，可以减少制造步骤的数量，并且可以缓和栅极绝缘膜上的栅电极与元件隔离膜上的配线之间的电平差。

10. 发明授权

US06307251B1 Semiconductor device having capacitance element and method of producing the same 有权
标题翻译：具有电容元件的半导体器件及其制造方法
公开(公告)号：US06307251B1
公开(公告)日：2001-10-23
申请号：US09444820
申请日：1999-11-22
申请人： Nobuyuki Sekikawa , Koichi Hirata , Wataru Andoh , Noriyasu Katagiri
发明人： Nobuyuki Sekikawa , Koichi Hirata , Wataru Andoh , Noriyasu Katagiri
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L27/1085 , H01L29/94
摘要： To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film (2) and the first polycrystalline silicon layer (3) are used as a stress buffering material at the time of formation of the element separation oxide film. These are not removed and used as the capacitance insulation film and a portion of the upper electrode of the capacitance element. Thereby, the removing process of the pad.polycrystalline silicon layer, and the dummy oxidation and its removing process in the conventional example, can be omitted and the process can be shortened. Further, a problem of the impurity enhanced oxidation at the time of formation of the capacitance insulation film can be solved.
摘要翻译：缩短具有电容元件的半导体器件的制造工序。在形成元件分离氧化膜时，将衬垫氧化膜（2）和第一多晶硅层（3）用作应力缓冲材料。这些不被去除并用作电容绝缘膜和电容元件的上部电极的一部分。由此，可以省略在多个实施例中的多晶硅层的去除处理以及虚拟氧化及其去除工艺，并且可以缩短处理。此外，可以解决在形成电容绝缘膜时杂质增强氧化的问题。

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