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1. 发明授权

US07028109B2 Data transfer control device including buffer controller with plurality of pipe regions allocated to plurality of endpoints 失效
标题翻译：数据传输控制装置包括具有分配给多个端点的多个管道区域的缓冲器控制器
公开(公告)号：US07028109B2
公开(公告)日：2006-04-11
申请号：US10377763
申请日：2003-03-04
申请人： Nobuyuki Saito , Shinsuke Kubota , Hiroaki Shimono , Kuniaki Matsuda
发明人： Nobuyuki Saito , Shinsuke Kubota , Hiroaki Shimono , Kuniaki Matsuda
IPC分类号： G06F3/00
CPC分类号： G06F13/4022
摘要： A plurality of pipe regions PIPE0 to PIPEe in which data transferred to and from endpoints is stored are allocated in a packet buffer (FIFO). Transfer condition information on data transfer between the pipe regions and the endpoints is set in transfer condition registers TREG0 to TREGe in a register section. A host (transfer) controller automatically generates a transaction for each of the endpoints based on the transfer condition information (total size, maximum packet size, transfer direction, number of continuous execution times, token issue interval, and the like) set in the transfer condition registers, and automatically transfers data between each pipe region and the endpoint. An OTG (state) controller which controls a state of USB On-The-Go is provided. The pipe regions are allocated in the packet buffer during a host operation.
摘要翻译：在存储分组缓冲器（FIFO）的情况下分配存储了从端点传送的数据的多个管道区域PIPE 0〜PIPEe。在管道区域和端点之间的数据传输的转移条件信息被设置在寄存器部分的传送条件寄存器TREG 0到TREGe中。主机（传输）控制器根据转移中设置的传送条件信息（总大小，最大包大小，传送方向，连续执行次数，令牌发放间隔等）自动生成每个端点的事务。条件寄存器，并在每个管道区域和端点之间自动传输数据。提供控制USB On-The-Go状态的OTG（状态）控制器。管道区域在主机操作期间被分配在分组缓冲器中。

2. 发明授权

US07428600B2 Data transfer control device, electronic equipment, and data transfer control method 失效
标题翻译：数据传输控制装置，电子设备和数据传输控制方法
公开(公告)号：US07428600B2
公开(公告)日：2008-09-23
申请号：US10377765
申请日：2003-03-04
申请人： Nobuyuki Saito , Shinsuke Kubota , Kuniaki Matsuda , Kenyou Nagao
发明人： Nobuyuki Saito , Shinsuke Kubota , Kuniaki Matsuda , Kenyou Nagao
IPC分类号： G06F3/00
CPC分类号： H04L49/9073 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9057 , H04L49/9078
摘要： When transfer condition information is set and the start of automatic control transfer is instructed, a transfer controller (host controller) automatically issues a setup stage transaction and automatically transfers a setup stage packet, then, if there is data to be transferred, it automatically issues a data stage transaction and automatically transfers a data stage packet. It then automatically issues a status stage transaction and automatically transfers a status stage packet. Device request data, the total size of transfer data, data stage present/absent information, transfer direction in the data stage, and maximum packet size are set in transfer condition registers. A pipe region is allocated in the packet buffer during host operation of USB On-The-Go.
摘要翻译：当传送条件信息被设置并且指示了自动控制转移的开始时，传送控制器（主机控制器）自动发出建立阶段事务并自动传送建立阶段分组，然后如果有要传送的数据，它将自动发出数据阶段交易并自动传输数据阶段数据包。然后它自动发出状态阶段事务并自动传送状态阶段数据包。在传送条件寄存器中设置设备请求数据，传输数据的总大小，数据级存在/不存在信息，数据级传输方向以及最大包大小。在USB On-The-Go的主机操作期间，分组缓冲区中分配管道区域。

3. 发明授权

US07024504B2 Data transfer control device, electronic equipment and data transfer control method 失效
公开(公告)号：US07024504B2
公开(公告)日：2006-04-04
申请号：US10376548
申请日：2003-03-04
申请人： Nobuyuki Saito , Shun Oshita , Shinsuke Kubota , Kuniaki Matsuda , Kenyou Nagao
发明人： Nobuyuki Saito , Shun Oshita , Shinsuke Kubota , Kuniaki Matsuda , Kenyou Nagao
IPC分类号： G06F13/00
CPC分类号： G06F13/4081
摘要： A signal state detection circuit of a data transfer control device notifies a processing of results detected by a line state detection circuit or a power supply line detection circuit by using an interrupt signal. The processing sets a state command corresponding to a state of a transition destination judged based on the notified detection results in a control register of a state controller. A state command decoder decodes the state command set in the control register and generates a control signal. A signal line control circuit controls a signal state of at least one of signal lines formed of data signal lines (D+ and D−) and power supply lines (VBUS and GND) based on the control signal.

4. 发明申请

US20050091564A1 Data transfer control device, electronic instrument, and data transfer control method 失效
标题翻译：数据传输控制装置，电子仪器和数据传输控制方法
公开(公告)号：US20050091564A1
公开(公告)日：2005-04-28
申请号：US10941826
申请日：2004-09-16
申请人： Shun Oshita , Shinsuke Kubota , Hiroaki Shimono
发明人： Shun Oshita , Shinsuke Kubota , Hiroaki Shimono
IPC分类号： G06F13/38 , H04L1/08 , H04L1/18 , H04L29/08
CPC分类号： H04L1/1887 , H04L1/1874
摘要： A data transfer control device for data transfer through a bus, includes: a buffer controller which controls access to a packet buffer which stores data; and a transfer controller which controls transfer of the data stored in the packet buffer. A transaction for performing data transfer with a transfer destination is issued, and when a negative acknowledgment (NAK) response to the issued transaction is returned from the transfer destination, issuance of a retransmission transaction for the NAK response is allowed after waiting for a predetermined skip timing.
摘要翻译：一种用于通过总线进行数据传输的数据传输控制装置，包括：控制对存储数据的分组缓冲器的访问的缓冲器控制器; 以及传送控制器，其控制存储在分组缓冲器中的数据的传送。发布用于执行与传送目的地的数据传输的事务，并且当从传送目的地返回对发出的事务的否定确认（NAK）响应时，在等待预定的跳过之后允许发送用于NAK响应的重传事务定时。

5. 发明授权

US07337382B2 Data transfer control device, electronic instrument, and data transfer control method 失效
标题翻译：数据传输控制装置，电子仪器和数据传输控制方法
公开(公告)号：US07337382B2
公开(公告)日：2008-02-26
申请号：US10941826
申请日：2004-09-16
申请人： Shun Oshita , Shinsuke Kubota , Hiroaki Shimono
发明人： Shun Oshita , Shinsuke Kubota , Hiroaki Shimono
IPC分类号： G08C25/02 , H04L1/18
CPC分类号： H04L1/1887 , H04L1/1874
摘要： A data transfer control device for data transfer through a bus, includes: a buffer controller which controls access to a packet buffer which stores data; and a transfer controller which controls transfer of the data stored in the packet buffer. A transaction for performing data transfer with a transfer destination is issued, and when a negative acknowledgment (NAK) response to the issued transaction is returned from the transfer destination, issuance of a retransmission transaction for the NAK response is allowed after waiting for a predetermined skip timing.
摘要翻译：一种用于通过总线进行数据传输的数据传输控制装置，包括：控制对存储数据的分组缓冲器的访问的缓冲器控制器; 以及传送控制器，其控制存储在分组缓冲器中的数据的传送。发布用于执行与传送目的地的数据传输的事务，并且当从传送目的地返回对发出的事务的否定确认（NAK）响应时，在等待预定的跳过之后允许发送用于NAK响应的重传事务定时。

6. 发明授权

US07359996B2 Data transfer control device, electronic equipment, and data transfer control method 失效
标题翻译：数据传输控制装置，电子设备和数据传输控制方法
公开(公告)号：US07359996B2
公开(公告)日：2008-04-15
申请号：US10377764
申请日：2003-03-04
申请人： Nobuyuki Saito , Shinsuke Kubota , Hironobu Kazama
发明人： Nobuyuki Saito , Shinsuke Kubota , Hironobu Kazama
IPC分类号： G06F13/28
CPC分类号： G06F13/385
摘要： Pipe regions PIPE0 to PIPEe (or endpoint regions) are allocated in a packet buffer, registers in which are set page sizes MPS0 to MPe (maximum packet size) and numbers of pages BP0 to BPe for the pipe regions are provided, and data is transferred between pipe regions and endpoints, region sizes RS0 to RSe of the pipe regions being set by the page sizes and numbers of pages. The page sizes and numbers of pages are set in registers that are used in common during both host operation and peripheral operation in accordance with the USB on-the-go standard. Transfer condition information such as transfer types TT0 to TTe is set in the registers, transactions with respect to the endpoints are automatically issued, and data is automatically transferred. Pipe regions are allocated in the packet buffer during host operation whereas endpoint regions are allocated during peripheral operation.
摘要翻译：管道区域PIPE 0至PIPEe（或端点区域）被分配在分组缓冲器中，其中设置了页面大小MPS 0至MPe（最大分组大小）和管道区域的页面BP 0至BPe的寄存器，并且数据在管道区域和端点之间传输，管道区域的区域大小RS 0至RSe由页面大小和页数设置。在主机操作和外设操作期间，根据USB移动标准，页面大小和页数设置在常用的寄存器中。转移条件信息如转移类型TT 0至TTe被设置在寄存器中，自动发出关于端点的交易，并自动传送数据。管道区域在主机操作期间分配在分组缓冲器中，而端点区域在外围操作期间被分配。

7. 发明授权

US07921334B2 Program and method for error determination, and electronic apparatus 失效
标题翻译：错误确定程序和方法以及电子设备
公开(公告)号：US07921334B2
公开(公告)日：2011-04-05
申请号：US12124214
申请日：2008-05-21
申请人： Shinsuke Kubota , Takayuki Ohtake
发明人： Shinsuke Kubota , Takayuki Ohtake
IPC分类号： G06F11/00
CPC分类号： G06F11/0751 , G06F11/073
摘要： There is provided an error determination program executed by an information processor included in an electronic apparatus that includes a device installation section capable of installing any one of a plurality of devices having different formats, a host controller acting as an intermediary between the information processor and the device installed in the device installation section, and a storage circuit storing an error determination information table that includes a plurality of pieces of error determination information for determining a presence or absence of any error in a plurality of responses to a plurality of commands from the devices installable in the device installation section, by associating the pieces of error determination information with a combination of the formats of the installable devices and the commands executable by the devices. The program includes instructing the host controller to issue a desired command in the commands executable by the device installed in the device installation section to the installed device; acquiring the error determination information associated with the combination of the format of the installed device and the desired command from the error determination information table; acquiring response content information regarding a content of a response to the desired command from the installed device from the host controller; and determining the presence or absence of any error in the response based on the error determination information and the response content information.
摘要翻译：提供了一种由包括在电子设备中的信息处理器执行的错误确定程序，该电子设备包括能够安装具有不同格式的多个设备中的任何一个的设备安装部分，作为信息处理器和装置安装在装置安装部分中的存储装置，以及存储电路的存储电路，所述存储电路包括多个错误判定信息，用于确定来自所述装置的多个命令的多个响应中存在或不存在任何错误通过将错误确定信息与可安装设备的格式和可由设备执行的命令的组合相关联来安装在设备安装部分中。该程序包括指示主机控制器在安装在设备安装部分中的设备执行的命令中向所安装的设备发出所需命令; 从所述错误判定信息表中获取与所安装的装置的格式的组合和所述期望命令相关联的所述错误确定信息; 从所述主机控制器获取关于来自所安装的设备的对所述期望命令的响应的内容的响应内容信息; 以及基于所述错误确定信息和所述响应内容信息来确定所述响应中是否存在任何错误。

8. 发明申请

US20080294945A1 PROGRAM AND METHOD FOR ERROR DETERMINATION, AND ELECTRONIC APPARATUS 失效
标题翻译：错误判定程序和方法，以及电子设备
公开(公告)号：US20080294945A1
公开(公告)日：2008-11-27
申请号：US12124214
申请日：2008-05-21
申请人： Shinsuke Kubota , Takayuki Ohtake
发明人： Shinsuke Kubota , Takayuki Ohtake
IPC分类号： G06F11/22
CPC分类号： G06F11/0751 , G06F11/073
摘要： There is provided an error determination program executed by an information processor included in an electronic apparatus that includes a device installation section capable of installing any one of a plurality of devices having different formats, a host controller acting as an intermediary between the information processor and the device installed in the device installation section, and a storage circuit storing an error determination information table that includes a plurality of pieces of error determination information for determining a presence or absence of any error in a plurality of responses to a plurality of commands from the devices installable in the device installation section, by associating the pieces of error determination information with a combination of the formats of the installable devices and the commands executable by the devices. The program includes instructing the host controller to issue a desired command in the commands executable by the device installed in the device installation section to the installed device; acquiring the error determination information associated with the combination of the format of the installed device and the desired command from the error determination information table; acquiring response content information regarding a content of a response to the desired command from the installed device from the host controller; and determining the presence or absence of any error in the response based on the error determination information and the response content information.
摘要翻译：提供了一种由包括在电子设备中的信息处理器执行的错误确定程序，该电子设备包括能够安装具有不同格式的多个设备中的任何一个的设备安装部分，作为信息处理器和装置安装在装置安装部分中的存储装置，以及存储电路的存储电路，所述存储电路包括多个错误判定信息，用于确定来自所述装置的多个命令的多个响应中存在或不存在任何错误通过将错误确定信息与可安装设备的格式和可由设备执行的命令的组合相关联来安装在设备安装部分中。该程序包括指示主机控制器在安装在设备安装部分中的设备执行的命令中向所安装的设备发出所需命令; 从所述错误判定信息表中获取与所安装的装置的格式的组合和所述期望命令相关联的所述错误确定信息; 从所述主机控制器获取关于来自所安装的设备的对所述期望命令的响应的内容的响应内容信息; 以及基于所述错误确定信息和所述响应内容信息来确定所述响应中是否存在任何错误。

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