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1. 发明申请

US20070182456A1 Reducing Pin Count When the Digital Output is to be Provided in Differential or Single-ended Form 审中-公开
标题翻译：当数字输出以差分或单端形式提供时，减少引脚数
公开(公告)号：US20070182456A1
公开(公告)日：2007-08-09
申请号：US11561424
申请日：2006-11-20
申请人： Nitin Agarwal , Eduardo Bartolome , Sandeep Oswal , Visvesvaraya Pentakota , Jagannathan Venkataraman , Nagarajan Viswanathan , Vinod Paliakara
发明人： Nitin Agarwal , Eduardo Bartolome , Sandeep Oswal , Visvesvaraya Pentakota , Jagannathan Venkataraman , Nagarajan Viswanathan , Vinod Paliakara
IPC分类号： H03K19/00
CPC分类号： H03K19/1732
摘要： An integrated circuit provides digital output signals in either single-ended or differential form on a shared set of pins. A control circuit generates signals to ensure that when one form (single-ended or differential) of outputs are being provided, outputs in the other form are disabled. Outputs in differential form may be provided at twice the frequency as compared to the outputs in single-ended form. As a result the same number of pins can be supported for both single-ended and differential outputs for a desired data throughput, and the pin count of the integrated circuit is reduced.
摘要翻译：集成电路在共享引脚组上提供单端或差分形式的数字输出信号。控制电路产生信号，以确保当提供输出的一个形式（单端或差分）时，另一种形式的输出被禁用。与单端形式的输出相比，差分形式的输出可以提供两倍的频率。因此，为了达到所需的数据吞吐量，单端和差分输出都可以支持相同数量的引脚，并且减少了集成电路的引脚数。

2. 发明申请

US20090091487A1 Spurious Free Dynamic Range Of An Analog To Digital Converter 审中-公开
标题翻译：模数转换器的无杂散动态范围
公开(公告)号：US20090091487A1
公开(公告)日：2009-04-09
申请号：US11867016
申请日：2007-10-04
申请人： Nagarajan Viswanathan , Nitin Agarwal , Jagannathan Venkataraman , Visvesvaraya Pentakota , Abhaya Kumar
发明人： Nagarajan Viswanathan , Nitin Agarwal , Jagannathan Venkataraman , Visvesvaraya Pentakota , Abhaya Kumar
IPC分类号： H03M1/44
CPC分类号： H03M1/0614 , H03M1/12
摘要： Removing an Nth harmonic (of a fundamental frequency) generated due to non-ideal ADC operation from the output of the ADC. In an embodiment, digital values containing in-phase and quadrature phase components of the Nth harmonic are generated using mathematical operations, scaled using scaling factors, and then subtracted from the (non-ideal) output of the ADC. A continuous-time derivative of the input signal used to generate the quadrature phase component, enabling a same set of scaling factors to be used for the same input irrespective of the sampling frequency. Spurious Free Dynamic Range of the ADC is thus improved.
摘要翻译：从ADC的输出消除由非理想ADC操作产生的第N次谐波（基频）。在一个实施例中，使用使用缩放因子缩放，然后从ADC的（非理想）输出中减去的数学运算来产生包含第N次谐波的同相和正交相位分量的数字值。用于产生正交相位分量的输入信号的连续时间导数，使得相同的一组缩放因子能够用于相同的输入，而与采样频率无关。因此，ADC的无杂散动态范围得到改善。

3. 发明申请

US20050116847A1 CALIBRATING CAPACITOR MISMATCH IN A PIPELINE ADC 有权
标题翻译：校准电容器在管道ADC中的误差
公开(公告)号：US20050116847A1
公开(公告)日：2005-06-02
申请号：US10722416
申请日：2003-11-28
申请人： Visvesvaraya Pentakota , Jagannathan Venkataraman , Vineet Mishra
发明人： Visvesvaraya Pentakota , Jagannathan Venkataraman , Vineet Mishra
IPC分类号： H03M1/10 , H03M1/16 , H04L20060101
CPC分类号： H03M1/109 , H03M1/168
摘要： An on-chip calibration circuit which can dynamically (i.e., in operational environment) measure the capacitor mismatch in an ADC using sampling capacitors to sample an input signal and a feedback capacitor (in combination with an amplifier) for amplification. The measured values can be used to generate accurate digital codes representing analog signal samples. The calibration circuit connects the capacitors to various voltage levels and measures the mismatch levels by examining various signals (e.g., the digital codes) generated in such situations.
摘要翻译：可以动态地（即在操作环境中）的片上校准电路使用采样电容器测量ADC中的电容器失配，以对放大的输入信号和反馈电容器（与放大器组合）进行采样。测量值可用于产生表示模拟信号样本的精确数字代码。校准电路将电容器连接到各种电压电平，并通过检查在这种情况下产生的各种信号（例如，数字代码）来测量失配水平。

4. 发明授权

US07885144B2 Time-dependant gain control for an amplifier used in receiving echoes 有权
标题翻译：用于接收回波的放大器的时间依赖增益控制
公开(公告)号：US07885144B2
公开(公告)日：2011-02-08
申请号：US12241075
申请日：2008-09-30
申请人： Sandeep Oswal , Jagannathan Venkataraman , Visvesvaraya Appala Pentakota , Shagun Dusad
发明人： Sandeep Oswal , Jagannathan Venkataraman , Visvesvaraya Appala Pentakota , Shagun Dusad
IPC分类号： G01S15/00
CPC分类号： G01S7/52033
摘要： An amplifier circuit to amplify a sequence of echoes and to generate a corresponding sequence of amplified signals. In an embodiment, the amplifier includes an operational amplifier, with variable input and feedback resistances such that the ratio of the two resistances can be controlled. A gain control block controls the ratio in a time dependent manner to obtain desired gain factors for each of the echoes. The gain factors can be pre-computed such that all the echoes are gained to the same level in case of an ultra-sound system.
摘要翻译：放大器电路，用于放大回波序列并产生相应的放大信号序列。在一个实施例中，放大器包括具有可变输入和反馈电阻的运算放大器，使得可以控制两个电阻的比率。增益控制块以时间依赖的方式控制比率，以获得每个回波的期望的增益因子。可以预先计算增益因子，使得在超声系统的情况下，所有回波都被获得到相同的水平。

5. 发明申请

US20100080083A1 Time-Dependant Gain Control For An Amplifier Used In Receiving Echoes 有权
标题翻译：用于接收回波的放大器的时间依赖增益控制
公开(公告)号：US20100080083A1
公开(公告)日：2010-04-01
申请号：US12241075
申请日：2008-09-30
申请人： Sandeep Oswal , Jagannathan Venkataraman , Visvesvaraya Appala Pentakota , Shagun Dusad
发明人： Sandeep Oswal , Jagannathan Venkataraman , Visvesvaraya Appala Pentakota , Shagun Dusad
IPC分类号： G01S15/00
CPC分类号： G01S7/52033
摘要： An amplifier circuit to amplify a sequence of echoes and to generate a corresponding sequence of amplified signals. In an embodiment, the amplifier includes an operational amplifier, with variable input and feedback resistances such that the ratio of the two resistances can be controlled. A gain control block controls the ratio in a time dependent manner to obtain desired gain factors for each of the echoes. The gain factors can be pre-computed such that all the echoes are gained to the same level in case of an ultra-sound system.
摘要翻译：放大器电路，用于放大回波序列并产生相应的放大信号序列。在一个实施例中，放大器包括具有可变输入和反馈电阻的运算放大器，使得可以控制两个电阻的比率。增益控制块以时间依赖的方式控制比率，以获得每个回波的期望的增益因子。可以预先计算增益因子，使得在超声系统的情况下，所有回波都被获得到相同的水平。

6. 发明申请

US20090257558A1 NOISE LIMITATION OF A SIGNAL DEPENDENT MULTIBIT DIGITAL TO ANALOG SIGNAL CONVERSION 有权
标题翻译：信号依赖多数字数字到模拟信号转换的噪声限制
公开(公告)号：US20090257558A1
公开(公告)日：2009-10-15
申请号：US12422304
申请日：2009-04-13
申请人： Sandeep Oswal , Jagannathan Venkataraman
发明人： Sandeep Oswal , Jagannathan Venkataraman
IPC分类号： H05G1/08 , H03M3/00
CPC分类号： H03M1/0665 , H03M1/806 , H03M3/464
摘要： Several methods and a system of noise limitation of a signal dependent multibit digital to analog signal conversion are disclosed. An exemplary embodiment provides a method that includes receiving an output of a multibit analog to digital circuit of a continuous time sigma delta converter. The method further includes limiting a noise generation by adaptively selecting a digital to analog converter element out of a plurality of digital to analog converter elements in accordance with an input signal magnitude. In addition, the method includes implementing a selected digital to analog converter element to generate an analog signal.
摘要翻译：公开了一种信号相关多位数字到模拟信号转换的几种方法和噪声限制系统。示例性实施例提供了一种方法，其包括接收连续时间Σ-Δ转换器的多位模拟数字电路的输出。该方法还包括根据输入信号幅度自适应地选择多个数模转换器元件中的数模转换器元件来限制噪声产生。此外，该方法包括实现所选择的数模转换器元件以产生模拟信号。

7. 发明授权

US07884746B2 Noise limitation of a signal dependent multibit digital to analog signal conversion 有权
标题翻译：信号相关多位数字到模拟信号转换的噪声限制
公开(公告)号：US07884746B2
公开(公告)日：2011-02-08
申请号：US12422304
申请日：2009-04-13
申请人： Sandeep Oswal , Jagannathan Venkataraman
发明人： Sandeep Oswal , Jagannathan Venkataraman
IPC分类号： H03M1/66
CPC分类号： H03M1/0665 , H03M1/806 , H03M3/464
摘要： Several methods and a system of noise limitation of a signal dependent multibit digital to analog signal conversion are disclosed. An exemplary embodiment provides a method that includes receiving an output of a multibit analog to digital circuit of a continuous time sigma delta converter. The method further includes limiting a noise generation by adaptively selecting a digital to analog converter element out of a plurality of digital to analog converter elements in accordance with an input signal magnitude. In addition, the method includes implementing a selected digital to analog converter element to generate an analog signal.
摘要翻译：公开了一种信号相关多位数字到模拟信号转换的几种方法和噪声限制系统。示例性实施例提供了一种方法，其包括接收连续时间Σ-Δ转换器的多位模拟数字电路的输出。该方法还包括根据输入信号幅度自适应地选择多个数模转换器元件中的数模转换器元件来限制噪声产生。此外，该方法包括实现所选择的数模转换器元件以产生模拟信号。

8. 发明授权

US07911256B2 Dual integrator circuit for analog front end (AFE) 有权
标题翻译：用于模拟前端（AFE）的双积分电路
公开(公告)号：US07911256B2
公开(公告)日：2011-03-22
申请号：US12541165
申请日：2009-08-14
申请人： Jagannathan Venkataraman , Vajeed Nimran , Sandeep Oswal , Visveswaraya Pentakota
发明人： Jagannathan Venkataraman , Vajeed Nimran , Sandeep Oswal , Visveswaraya Pentakota
IPC分类号： H03K5/00
CPC分类号： H03F3/087 , H03F1/083 , H03F3/45475 , H03F2203/45138 , H03F2203/45534 , H03K5/1252
摘要： A circuit includes a generating circuit that generates a current signal in response to an input signal, a first one of a plurality of integrators that generates a voltage signal from the current signal, a comparator that is responsive to the voltage signal to compare the voltage signal with a predefined voltage, a switching circuit that reconfigures a first capacitor and a second capacitor connected to the first one of the plurality of integrators to discharge the first capacitor and to enable the second capacitor to generate the voltage signal in response to the current signal, and an analog-to-digital converter to generate an output when a predefined time interval has elapsed. The output is obtained by adding a first charge value corresponding to a count of number of times the voltage signal reaches the predefined voltage in the predefined time interval and a second charge value from the analog-to-digital converter.
摘要翻译：电路包括产生电路以响应于输入信号产生电流信号，多个积分器中的第一个从当前信号产生电压信号;响应于电压信号比较电压信号的比较器具有预定电压的开关电路，重新配置连接到所述多个积分器中的所述第一电容器的第一电容器和第二电容器以对所述第一电容器进行放电并使得所述第二电容器能够响应于所述电流信号而产生所述电压信号，以及当经过预定时间间隔时产生输出的模拟 - 数字转换器。通过将与电压信号达到预定电压的次数的计数相对应的第一充电值与来自模数转换器的第二充电值相加来获得输出。

9. 发明申请

US20080036632A1 SIGNAL-TO-NOISE RATIO WHEN USING FEWER BITS THAN THE NUMBER OF OUTPUT BITS OF AN ANALOG TO DIGITAL CONVERTER 有权
标题翻译：当使用更少的位数比模拟数字转换器的输出位数多的信号噪声比
公开(公告)号：US20080036632A1
公开(公告)日：2008-02-14
申请号：US11836163
申请日：2007-08-09
申请人： Nagarajan Viswanathan , Jagannathan Venkataraman , Ganesh Kiran
发明人： Nagarajan Viswanathan , Jagannathan Venkataraman , Ganesh Kiran
IPC分类号： H03M3/00
CPC分类号： H03M7/3042 , H03M7/3026
摘要： Improving signal-to-noise ratio (SNR) when using fewer bits than the number of output bits of an ADC as digital representation of the strength of the samples of an input signal. In an embodiment, an ADC generates digital values of H bits by sampling an input signal at corresponding time instances. An error signal representing the (H-N) least significant bits of the H-bit digital values is processed to determine respective filtered values, which are respectively added to the corresponding ones of the H-bit digital values. The (H-N) bits of the resulting added values are dropped to generate N bit values. The N bit values thus generated may have improved SNR at least in a band of interest, as desired.
摘要翻译：当使用比ADC的输出位数更少的位作为输入信号样本强度的数字表示时，提高信噪比（SNR）。在一个实施例中，ADC通过在相应的时间实例对输入信号进行采样来产生H位的数字值。处理表示H位数字值的（H-N）最低有效位的错误信号，以确定相应的滤波值，它们分别加到相应的H位数字值中。所产生的相加值的（H-N）位被丢弃以产生N位值。如此产生的N位值至少可以根据需要在感兴趣的频带中具有改善的SNR。

10. 发明授权

US07425911B2 Signal-to-noise ratio when using fewer bits than the number of output bits of an analog to digital converter 有权
标题翻译：当使用比模数转换器的输出位数更少的位时，信噪比
公开(公告)号：US07425911B2
公开(公告)日：2008-09-16
申请号：US11836163
申请日：2007-08-09
申请人： Nagarajan Viswanathan , Jagannathan Venkataraman , Ganesh Kiran
发明人： Nagarajan Viswanathan , Jagannathan Venkataraman , Ganesh Kiran
IPC分类号： H03M3/00
CPC分类号： H03M7/3042 , H03M7/3026
摘要： Improving signal-to-noise ratio (SNR) when using fewer bits than the number of output bits of an ADC as digital representation of the strength of the samples of an input signal. In an embodiment, an ADC generates digital values of H bits by sampling an input signal at corresponding time instances. An error signal representing the (H-N) least significant bits of the H-bit digital values is processed to determine respective filtered values, which are respectively added to the corresponding ones of the H-bit digital values. The (H-N) bits of the resulting added values are dropped to generate N bit values. The N bit values thus generated may have improved SNR at least in a band of interest, as desired.
摘要翻译：当使用比ADC的输出位数更少的位作为输入信号样本强度的数字表示时，提高信噪比（SNR）。在一个实施例中，ADC通过在相应的时间实例对输入信号进行采样来产生H位的数字值。处理表示H位数字值的（H-N）最低有效位的错误信号，以确定相应的滤波值，它们分别加到相应的H位数字值中。所产生的相加值的（H-N）位被丢弃以产生N位值。如此产生的N位值至少可以根据需要在感兴趣的频带中具有改善的SNR。

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