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1. 发明授权

US10110328B2 Apparatus and methods for calibrating analog circuitry in an integrated circuit 有权
公开(公告)号：US10110328B2
公开(公告)日：2018-10-23
申请号：US13446555
申请日：2012-04-13
申请人： Neville Carvalho , Tim Tri Hoang , Sergey Shumarayev
发明人： Neville Carvalho , Tim Tri Hoang , Sergey Shumarayev
IPC分类号： G01R35/00 , H04B17/21 , H04B17/11 , G12B13/00
摘要： The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

2. 发明授权

US09559881B2 Transceiver system with reduced latency uncertainty 有权
标题翻译：收发器系统具有降低的延迟不确定性
公开(公告)号：US09559881B2
公开(公告)日：2017-01-31
申请号：US12283652
申请日：2008-09-15
申请人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
发明人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
IPC分类号： H04L7/00 , H04B1/38 , H04L25/14
CPC分类号： H04L25/14
摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.
摘要翻译：描述了具有降低的等待时间不确定性的收发机系统。在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

3. 发明申请

US20090161738A1 Transceiver system with reduced latency uncertainty 有权
标题翻译：收发器系统具有降低的延迟不确定性
公开(公告)号：US20090161738A1
公开(公告)日：2009-06-25
申请号：US12283652
申请日：2008-09-15
申请人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
发明人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
IPC分类号： H04L7/00 , H04B1/38
CPC分类号： H04L25/14
摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.
摘要翻译：描述了具有降低的等待时间不确定性的收发机系统。在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

4. 发明授权

US08595670B1 Method and apparatus for circuit block reconfiguration EDA 有权
标题翻译：电路块重构EDA的方法和装置
公开(公告)号：US08595670B1
公开(公告)日：2013-11-26
申请号：US12719298
申请日：2010-03-08
申请人： John Tse , Neville Carvalho
发明人： John Tse , Neville Carvalho
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5045 , G06F17/5068
摘要： Methods and apparatus are described for efficiently performing EDA processing to arrive at a hardware definition for a varying fraction of a large circuit design. EDA processing is conducted targeting a pseudo hardware device with sufficient capacity to embody circuitry for the varying fraction, but substantially less than the true hardware target. The novel methods and apparatus may be beneficially employed to produce reconfiguration information for circuits that include programmable logic, for example.
摘要翻译：描述了用于有效执行EDA处理以达到大电路设计的不同部分的硬件定义的方法和装置。对具有足够容量的伪硬件设备进行EDA处理，以实现不同部分的电路，但是实质上小于真正的硬件目标。可以有益地使用新颖的方法和装置来产生例如包括可编程逻辑的电路的重新配置信息。

5. 发明授权

US08183883B1 Integrated circuit reconfiguration techniques 有权
标题翻译：集成电路重构技术
公开(公告)号：US08183883B1
公开(公告)日：2012-05-22
申请号：US12762295
申请日：2010-04-16
申请人： Chee Seng Tan , Chai Sia Tan , Elden Chau , John Tse , Neville Carvalho
发明人： Chee Seng Tan , Chai Sia Tan , Elden Chau , John Tse , Neville Carvalho
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1776 , G06F17/5054
摘要： A memory configuration circuit is provided. The memory configuration circuit may be integrated into a programmable logic device (PLD) and as such, may be used to configure and reconfigure specific elements in the PLD. The memory configuration circuit includes a comparator circuit and a counter. The comparator circuit is coupled to receive two data words from two different memory configuration sources. The comparator circuit compares the two data words received before writing one of the data words to a configuration memory. One of the data words may be written to the configuration memory if the two data words compared are not equal. The counter increments the address of the memory configuration sources so that a next data word can be processed after the current data word is processed.
摘要翻译：提供存储器配置电路。存储器配置电路可以集成到可编程逻辑器件（PLD）中，并且因此可用于配置和重新配置PLD中的特定元件。存储器配置电路包括比较器电路和计数器。比较器电路被耦合以从两个不同的存储器配置源接收两个数据字。比较器电路将在将一个数据字写入之前接收的两个数据字与配置存储器进行比较。如果所比较的两个数据字不相等，则可以将一个数据字写入配置存储器。计数器增加存储器配置源的地址，以便在处理当前数据字之后处理下一个数据字。

6. 发明授权

US08334716B1 Digital phase detection circuit and method 有权
标题翻译：数字相位检测电路及方法
公开(公告)号：US08334716B1
公开(公告)日：2012-12-18
申请号：US12580175
申请日：2009-10-15
申请人： Allan Thomas Davidson , Marwan A. Khalaf , Daniel Bowersox , Michael Menghui Zheng , Neville Carvalho
发明人： Allan Thomas Davidson , Marwan A. Khalaf , Daniel Bowersox , Michael Menghui Zheng , Neville Carvalho
IPC分类号： H03K3/00
CPC分类号： H03L7/085 , G11C7/222 , H03L7/0812
摘要： A digital phase detector circuit and corresponding monitor and control logic is presented. The digital phase detector has two storage elements, where the data input of the first storage element receives a first clock signal and the data input of the second storage element receives a second clock signal. A time shifter shifts the second clock signal by a shift period, and transmits the shifted signal to the clock input of the storage elements. The signals applied to the data inputs are transmitted from the storage elements when the clock input receives the shifted second clock signal from the time shifter. A monitor and control module samples the data output from the storage elements after each shifted second clock signal is transmitted by the time shifter. The sampling of the output data provides the data used to determine the time relationship between the first and the second clock signals.
摘要翻译：提出了一种数字相位检测电路及相应的监控与控制逻辑。数字相位检测器具有两个存储元件，其中第一存储元件的数据输入接收第一时钟信号，并且第二存储元件的数据输入接收第二时钟信号。时移器将第二时钟信号移位移位周期，并将移位的信号发送到存储元件的时钟输入。当时钟输入从时移器接收到移位的第二时钟信号时，从存储元件发送施加到数据输入端的信号。每个移位的第二个时钟信号由时间移位器发送之后，监视器和控制模块对从存储元件输出的数据进行采样。输出数据的采样提供用于确定第一和第二时钟信号之间的时间关系的数据。

7. 发明授权

US07724598B1 Megafunction block and interface 有权
标题翻译：宏功能块和接口
公开(公告)号：US07724598B1
公开(公告)日：2010-05-25
申请号：US11737654
申请日：2007-04-19
申请人： Vinson Chan , Chong H. Lee , Binh Ton , Thiagaraja Gopalsamy , Marcel A. LeBlanc , Neville Carvalho
发明人： Vinson Chan , Chong H. Lee , Binh Ton , Thiagaraja Gopalsamy , Marcel A. LeBlanc , Neville Carvalho
IPC分类号： G11C7/00
CPC分类号： G06F12/0292 , G06F12/0623 , G06F2212/1048
摘要： A megafunction block is provided that includes a serial interface enabling a user to specify settings of a configurable block of a programmable logic device. The megafunction block includes a register array having the capability of translating address information into actual addresses for a memory of the configurable block. Thus, as future configurations/standards are developed that a programmable logic device with the megafunction block will interfaces with, the settings for interfacing with the standards may be added to the register array. Consequently, the pin count will not need to increase as the megafunction block is scalable through the register map. Control logic verifies that the translated address is a valid address and the control logic will generate a selection signal based on whether a read or write operation is to be performed.
摘要翻译：提供了一种宏功能块，其包括使得用户能够指定可编程逻辑器件的可配置块的设置的串行接口。宏功能块包括具有将地址信息转换成可配置块的存储器的实际地址的能力的寄存器阵列。因此，随着具有宏功能块的可编程逻辑器件将与之相接的未来配置/标准被开发，用于与标准接口的设置可被添加到寄存器阵列中。因此，引脚数不需要增加，因为宏功能块可通过寄存器映射进行扩展。控制逻辑验证翻译的地址是否是有效地址，并且控制逻辑将基于是执行读操作还是写操作来生成选择信号。

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