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1. 发明授权

US08739009B1 Methods and apparatus for defect detection and correction via iterative decoding algorithms 有权
标题翻译：用于通过迭代解码算法进行缺陷检测和校正的方法和装置
公开(公告)号：US08739009B1
公开(公告)日：2014-05-27
申请号：US12328561
申请日：2008-12-04
申请人： Nedeljko Varnica , Yifei Zhang , Panu Chaichanavong , Gregory Burd
发明人： Nedeljko Varnica , Yifei Zhang , Panu Chaichanavong , Gregory Burd
IPC分类号： G06F11/00
CPC分类号： G06F11/0763 , G11B20/1833 , G11B2020/185 , H03M13/1111 , H03M13/2957 , H03M13/373 , H03M13/4138 , H03M13/6325 , H03M13/6343
摘要： In iterative decoding, a data recovery scheme corrects for corrupted or defective data by determining reliability metrics for blocks of decoded data. Block or windowed detectors generate block reliability metrics for data blocks (rather than individual bits) of decoded data using soft information from the regular decoding mode or from new iterative decoding iterations performed during error recovery mode. An error recovery system triggers corrective decoding of selected data blocks based on the block reliability metrics, by for example, comparing the block reliability metrics to a threshold or by selecting an adjustable number of the least reliable data blocks.
摘要翻译：在迭代解码中，数据恢复方案通过确定解码数据块的可靠性度量来校正损坏或缺陷数据。块或窗口检测器使用来自常规解码模式的软信息或在错误恢复模式期间执行的新的迭代解码迭代来生成解码数据的数据块（而不是单独位）的块可靠性度量。错误恢复系统通过例如将块可靠性度量与阈值进行比较或者通过选择可调节数量的最不可靠的数据块来触发基于块可靠性度量来对所选数据块的校正解码。

2. 发明授权

US08230312B1 Iterative decoder memory arrangement 有权
标题翻译：迭代解码器存储器布置
公开(公告)号：US08230312B1
公开(公告)日：2012-07-24
申请号：US12350885
申请日：2009-01-08
申请人： Engling Yeo , Panu Chaichanavong , Nedeljko Varnica , Gregory Burd , Zining Wu
发明人： Engling Yeo , Panu Chaichanavong , Nedeljko Varnica , Gregory Burd , Zining Wu
IPC分类号： H03M13/03
CPC分类号： H03M13/1117 , H03M13/114 , H03M13/116 , H03M13/2957 , H03M13/4138 , H03M13/6325 , H03M13/6343 , H03M13/6561
摘要： The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. In some implementations, an apparatus includes a memory module to communicate with an iterative code decoder. The memory module includes a single R memory component to store R data associated with a current codeword, and R data associated with a previous codeword. The memory module includes a Q memory component to store Q data associated with the current codeword, and Q data associated with the previous codeword. The memory module includes a channel detector memory component to store channel extrinsic information.
摘要翻译：本公开包括与迭代解码器存储器布置相关的装置，系统和技术。在一些实现中，装置包括与迭代码解码器通信的存储器模块。存储器模块包括用于存储与当前码字相关联的R数据的单个R存储器组件和与先前码字相关联的R数据。存储器模块包括用于存储与当前码字相关联的Q数据的Q存储器组件和与先前码字相关联的Q数据。存储器模块包括用于存储信道外在信息的信道检测器存储器组件。

3. 发明申请

US20090150746A1 ITERATIVE DECODER SYSTEMS AND METHODS 有权
标题翻译：迭代解码器系统和方法
公开(公告)号：US20090150746A1
公开(公告)日：2009-06-11
申请号：US12329581
申请日：2008-12-06
申请人： Panu Chaichanavong , Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
发明人： Panu Chaichanavong , Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
IPC分类号： H03M13/05 , G06F11/07
CPC分类号： H03M13/41 , G11B20/1426 , G11B20/1803 , G11B2020/10759 , G11B2020/1457 , H03M13/09 , H03M13/1105 , H03M13/1111 , H03M13/1114 , H03M13/13 , H03M13/29 , H03M13/2948 , H03M13/3746 , H03M13/4146 , H03M13/6343 , H03M13/6502 , H03M13/6561
摘要： Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. This may allow for a 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.
摘要翻译：提供了系统和方法，用于改进迭代解码器系统的设计和性能。在一些实施例中，迭代解码器可以通过FIR RAM从FIR样本去耦，从而导致较不复杂的设计和较短的处理时间。在一些实施例中，当在迭代解码器的SOVA和LDPC之间传递信息时，可以使用中间存储器。在一些实施例中，可以在每次LDPC迭代期间从从LDPC接收的信息中连续序列化所需的SOVA信息。在一些实施例中，HR RLL编码器的1 /（1 + D2）预编码器可以被分成两个串行，1 /（1 + D）个预编码器。一个1 /（1 + D）预编码器可以被拉出HR RLL编码器外部并与迭代解码器结合使用。这可以允许可以与迭代解码器一起使用的1 /（1 + D）预编码器，同时保持由HR RLL编码器对编码信息施加的RLL约束。

4. 发明授权

US08522123B1 Iterative decoder memory arrangement 有权
标题翻译：迭代解码器存储器布置
公开(公告)号：US08522123B1
公开(公告)日：2013-08-27
申请号：US13556063
申请日：2012-07-23
申请人： Engling Yeo , Panu Chaichanavong , Nedeljko Varnica , Gregory Burd , Zining Wu
发明人： Engling Yeo , Panu Chaichanavong , Nedeljko Varnica , Gregory Burd , Zining Wu
IPC分类号： H03M13/03
CPC分类号： H03M13/1117 , H03M13/114 , H03M13/116 , H03M13/2957 , H03M13/4138 , H03M13/6325 , H03M13/6343 , H03M13/6561
摘要： The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. A described apparatus includes a single R memory component including R banks, a Q memory component including Q banks, a channel detector memory component to store channel extrinsic information associated with current and previous codewords, and an iterative decoder communicatively coupled with the single R memory component, the Q memory component, and the channel detector memory component. The apparatus can be configured to alternate among the R banks for storing R data associated with a current codeword. The apparatus can be configured to alternate among the Q banks for storing Q data associated with a current codeword.
摘要翻译：本公开包括与迭代解码器存储器布置相关的装置，系统和技术。所描述的装置包括包括R组的单个R存储器组件，包括Q组的Q存储器组件，用于存储与当前和先前码字相关联的频道外在信息的信道检测器存储器组件，以及与单个R存储器组件通信耦合的迭代解码器，Q存储器组件和通道检测器存储器组件。该装置可以被配置为在R组之间交替存储用于存储与当前码字相关联的R数据。该装置可以被配置为在Q组之间交替存储用于存储与当前码字相关联的Q数据。

5. 发明授权

US08307268B2 Iterative decoder systems and methods 有权
标题翻译：迭代解码器系统和方法
公开(公告)号：US08307268B2
公开(公告)日：2012-11-06
申请号：US12329581
申请日：2008-12-06
申请人： Panu Chaichanavong , Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
发明人： Panu Chaichanavong , Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
IPC分类号： G06F11/00
CPC分类号： H03M13/41 , G11B20/1426 , G11B20/1803 , G11B2020/10759 , G11B2020/1457 , H03M13/09 , H03M13/1105 , H03M13/1111 , H03M13/1114 , H03M13/13 , H03M13/29 , H03M13/2948 , H03M13/3746 , H03M13/4146 , H03M13/6343 , H03M13/6502 , H03M13/6561
摘要： Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. This may allow for a 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.
摘要翻译：提供了系统和方法，用于改进迭代解码器系统的设计和性能。在一些实施例中，迭代解码器可以通过FIR RAM从FIR样本去耦，从而导致较不复杂的设计和较短的处理时间。在一些实施例中，当在迭代解码器的SOVA和LDPC之间传递信息时，可以使用中间存储器。在一些实施例中，可以在每次LDPC迭代期间从从LDPC接收的信息中连续序列化所需的SOVA信息。在一些实施例中，HR RLL编码器的1 /（1 + D2）预编码器可以被分成两个串行1 /（1 + D）个预编码器。一个1 /（1 + D）预编码器可以被拉出HR RLL编码器外部并与迭代解码器结合使用。这可以允许可以与迭代解码器一起使用的1 /（1 + D）预编码器，同时保持由HR RLL编码器对编码信息施加的RLL约束。

6. 发明授权

US08751912B1 Layered low density parity check decoder 有权
标题翻译：分层低密度奇偶校验解码器
公开(公告)号：US08751912B1
公开(公告)日：2014-06-10
申请号：US12987419
申请日：2011-01-10
申请人： Nedeljko Varnica , Panu Chaichanavong , Heng Tang
发明人： Nedeljko Varnica , Panu Chaichanavong , Heng Tang
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： H03M13/1105 , H03M13/036 , H03M13/1128 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/1162 , H03M13/6505 , H04L1/0051 , H04L1/0057
摘要： Apparatuses and methods associated with instant syndrome computation in a layered LDPC decoder are described. According to one embodiment, an apparatus includes a plurality of hardware layers, where a hardware layer is configured to compute a syndrome value from one or more bit values in the codeword. The apparatus includes a plurality of physical memories configured to store a plurality of syndrome values, where a physical memory is configured to store syndrome values computed by one or more hardware layers. The apparatus includes circuitry configured to simultaneously store a syndrome value computed by a hardware layer in physical memories associated with a bit in the codeword. The apparatus includes a decode logic configured to signal successful decoding of the codeword based, at least in part, on determining that a set of syndromes are satisfied based on values stored in the plurality of physical memories.
摘要翻译：描述了在分层LDPC解码器中与即时综合征计算相关联的装置和方法。根据一个实施例，一种装置包括多个硬件层，其中硬件层被配置为从码字中的一个或多个位值计算校正子值。该装置包括多个物理存储器，被配置为存储多个校正子值，其中物理存储器被配置为存储由一个或多个硬件层计算的校正子值。该装置包括被配置为同时存储由硬件层计算的与在码字中的位相关联的物理存储器中的校正子值的电路。该装置包括解码逻辑，其被配置为基于至少部分地基于基于存储在多个物理存储器中的值来确定一组校正子来满足码字的成功解码。

7. 发明授权

US08255764B1 Embedded parity coding for data storage 有权
标题翻译：用于数据存储的嵌入式奇偶编码
公开(公告)号：US08255764B1
公开(公告)日：2012-08-28
申请号：US11827206
申请日：2007-07-11
申请人： Engling Yeo , Eugene Pan , Henri Sutioso , Jun Xu , Shaohua Yang , Panu Chaichanavong , Gregory Burd , Zining Wu
发明人： Engling Yeo , Eugene Pan , Henri Sutioso , Jun Xu , Shaohua Yang , Panu Chaichanavong , Gregory Burd , Zining Wu
IPC分类号： H03M13/00
CPC分类号： H03M13/6362 , H03M5/145 , H03M13/1128 , H03M13/116 , H03M13/1515 , H03M13/2906 , H03M13/2915 , H03M13/31 , H03M13/6343
摘要： A decoder system comprises a tensor-product code (TPC) decoder that decodes a received data stream to generate a decoded signal. A mark module that replaces low-density parity check (LDPC) parity bits of the decoded signal with 0s to generate a reset output signal. A deinterleave module deinterleaves error correction parity bits that are within the reset output signal to generate a deinterleaved signal that comprises a decoded portion and a concatenated portion. The concatenated portion comprises the error correction parity bits. A parity decoder module removes the concatenated portion from the deinterleaved signal.
摘要翻译：解码器系统包括对接收的数据流进行解码以产生解码信号的张量乘积码（TPC）解码器。标记模块，用0替换解码信号的低密度奇偶校验位（LDPC）奇偶校验位，以产生复位输出信号。解交织模块对位于复位输出信号内的错误校正奇偶校验位进行解交织，以生成包含解码部分和级联部分的去交错信号。连接部分包括纠错奇偶校验位。奇偶校验解码器模块从去交织的信号中去除级联部分。

8. 发明授权

US08145983B1 Methods and apparatus for identification of likely errors in data blocks 有权
标题翻译：用于识别数据块中可能的错误的方法和装置
公开(公告)号：US08145983B1
公开(公告)日：2012-03-27
申请号：US11936578
申请日：2007-11-07
申请人： Panu Chaichanavong , Gregory Burd
发明人： Panu Chaichanavong , Gregory Burd
IPC分类号： H03M13/03
CPC分类号： H03M13/2933 , G11B2020/1836 , G11B2020/1859 , G11B2020/1863 , H03M13/098 , H03M13/373 , H03M13/3784 , H03M13/3994
摘要： Methods and apparatus are provided for processing a plurality of data blocks. In accordance with embodiments of the invention, a correction flag for each of the data blocks can be received, along with information on at least one error event for each of the data blocks. Using this received information, a search trellis corresponding to the data blocks can be determined. Determining the search trellis can include determining a plurality of branches and computing a branch metric for each of the branches. A search on the search trellis can be performed to identify at most one error event for each data block, where the search is based on the branch metrics.
摘要翻译：提供了用于处理多个数据块的方法和装置。根据本发明的实施例，可以接收每个数据块的校正标志以及关于每个数据块的至少一个错误事件的信息。使用该接收到的信息，可以确定与数据块相对应的搜索网格。确定搜索网格可以包括确定多个分支并且计算每个分支的分支度量。可以执行对搜索网格的搜索，以针对每个数据块最多识别一个错误事件，其中搜索基于分支度量。

9. 发明授权

US08054207B1 Enumerative DC-RLL constrained coding 有权
标题翻译：枚举DC-RLL约束编码
公开(公告)号：US08054207B1
公开(公告)日：2011-11-08
申请号：US12958713
申请日：2010-12-02
申请人： Panu Chaichanavong , Gregory Burd
发明人： Panu Chaichanavong , Gregory Burd
IPC分类号： H03M7/00
CPC分类号： H03M5/145
摘要： Systems and methods are provided for encoding and decoding constrained codewords using an enumerative coding graph. The constrained codewords may contain run-length and DC level limits. The enumerative coding graph contains a series of states and each state has multiple branches that lead to other states. Each state in the enumerative coding graph is associated with at least two bits of an enumerative codeword. Configuring the structure of the graph and cardinalities associated with each state allows the encoder to generate a code that conforms to defined constraints.
摘要翻译：提供了使用枚举编码图对受限码字进行编码和解码的系统和方法。约束码字可以包含游程长度和直流电平限制。枚举编码图包含一系列状态，每个状态具有导致其他状态的多个分支。枚举编码图中的每个状态与枚举码字的至少两个位相关联。配置与每个状态相关联的图形和基数的结构允许编码器生成符合规定约束的代码。

10. 发明授权

US08015224B1 Entropy source for random number generation 有权
标题翻译：随机数生成的熵源
公开(公告)号：US08015224B1
公开(公告)日：2011-09-06
申请号：US11949487
申请日：2007-12-03
申请人： Panu Chaichanavong , Tze Lei Poo , Zining Wu , Saeed Azimi , Gregory Burd
发明人： Panu Chaichanavong , Tze Lei Poo , Zining Wu , Saeed Azimi , Gregory Burd
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H04L9/0861
摘要： In a device having a data channel, in which random numbers are needed, such as a data storage device that uses random numbers to generate keys for cryptographic applications, random numbers are generated by a deterministic random bit generator seeded by bits derived from noise on the channel itself. The bits may be extracted from the least significant bits of the data signal after it is digitized, because those bits correspond to the noise in the signal. The extraction may occur immediately after digitization, or after subsequent filtering. A data signal emulator may be provided to simulate a data signal if a seed is required at a time when there is no data activity on the channel. The extracted bits may be post-processed to remove bias before the seed is provided to the deterministic random bit generator.
摘要翻译：在具有需要随机数的数据信道的装置中，例如使用随机数生成加密应用密钥的数据存储装置，随机数是由确定性随机比特发生器产生的，该确定性随机比特发生器由频道本身。在数字信号被数字化之后，可以从数据信号的最低有效位中提取位，因为这些位对应于信号中的噪声。提取可能在数字化后立即进行，或在后续过滤之后发生。如果在通道上没有数据活动的时候需要种子，则可以提供数据信号仿真器来模拟数据信号。提取的比特可以在将种子提供给确定性随机比特发生器之前进行后处理以去除偏差。

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