会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明申请
    • Apparatus, System, And Method For Matching Patterns With An Ultra Fast Check Engine
    • 用超快速检测引擎匹配模式的装置,系统和方法
    • US20120143889A1
    • 2012-06-07
    • US13309369
    • 2011-12-01
    • Bertrand F. CambouNeal BergerMourad El Baraji
    • Bertrand F. CambouNeal BergerMourad El Baraji
    • G06F17/30
    • G06F11/08G06F7/02G06F2207/025G11C11/1673G11C11/1675G11C11/5607G11C15/02G11C15/046
    • A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.
    • 检查引擎包括多个比较器,每个比较器包括对齐以存储包括在一组参考比特中的至少一个参考比特的第一方向特性,以及对准以呈现包括在一组目标比特中的至少一个目标比特的第二方向特性 。 多个比较器中的每一个被配置为基于第一方向特性和第二方向特性之间的相对对准来产生表示所述至少一个目标位和所述至少一个参考位之间的匹配水平的输出。 检查引擎被配置为使得多个比较器的输出被组合以产生组合输出。 检查引擎被配置为基于多个比较器的组合输出来确定目标比特的集合与参考比特集匹配。
    • 4. 发明授权
    • Apparatus, system, and method for matching patterns with an ultra fast check engine
    • 用于匹配模式与超快速检查引擎的装置,系统和方法
    • US08717794B2
    • 2014-05-06
    • US13309369
    • 2011-12-01
    • Bertrand F. CambouNeal BergerMourad El Baraji
    • Bertrand F. CambouNeal BergerMourad El Baraji
    • G11C15/02
    • G06F11/08G06F7/02G06F2207/025G11C11/1673G11C11/1675G11C11/5607G11C15/02G11C15/046
    • A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.
    • 检查引擎包括多个比较器,每个比较器包括对齐以存储包括在一组参考比特中的至少一个参考比特的第一方向特性,以及对准以呈现包括在一组目标比特中的至少一个目标比特的第二方向特性 。 多个比较器中的每一个被配置为基于第一方向特性和第二方向特性之间的相对对准来产生表示所述至少一个目标位和所述至少一个参考位之间的匹配水平的输出。 检查引擎被配置为使得多个比较器的输出被组合以产生组合输出。 检查引擎被配置为基于多个比较器的组合输出来确定目标比特的集合与参考比特集匹配。
    • 5. 发明授权
    • Method for writing in a MRAM-based memory device with reduced power consumption
    • 在基于MRAM的存储器件中写入功耗降低的方法
    • US08441844B2
    • 2013-05-14
    • US13155669
    • 2011-06-08
    • Mourad El BarajiNeal Berger
    • Mourad El BarajiNeal Berger
    • G11C11/00
    • G11C8/08G11C11/1673G11C11/1675
    • A method of writing in a memory device comprising a plurality of MRAM cells, each cell including a magnetic tunnel junction having a resistance that can be varied during a write operation when heated at a high threshold temperature; a plurality of word lines connecting cells along a row; and a plurality of bit lines connecting cells along a column; the method comprising supplying a bit line voltage to one of the bit lines and a word line voltage to one of the word lines for passing a heating current through the magnetic tunnel junction of a selected cell; said word line voltage is a word line overdrive voltage being higher than the core operating voltage of the cells such that the heating current has a magnitude that is high enough for heating the magnetic tunnel junction at the predetermined high threshold temperature. The memory device can be written with low power consumption.
    • 一种在包括多个MRAM单元的存储器件中写入的方法,每个单元包括具有在写入操作期间可以在高阈值温度下加热时可改变的电阻的磁性隧道结; 沿着一行连接单元的多个字线; 以及沿着列连接单元的多个位线; 该方法包括向位线之一提供位线电压,并将字线电压提供给一条字线,以使加热电流通过选定单元的磁性隧道结; 所述字线电压是字线过驱动电压高于电池的核心工作电压,使得加热电流具有足够高的程度,以在预定的高阈值温度下加热磁性隧道结。 可以以低功耗写入存储器件。
    • 8. 发明申请
    • NON-VOLATILE LOGIC DEVICES USING MAGNETIC TUNNEL JUNCTIONS
    • 使用磁性隧道结的非易失性逻辑器件
    • US20100302832A1
    • 2010-12-02
    • US12784848
    • 2010-05-21
    • Neal BergerMourad El Baraji
    • Neal BergerMourad El Baraji
    • G11C19/00
    • G11C19/08G11C8/04G11C11/1675G11C14/0081G11C19/02
    • The present disclosures concerns a register cell comprising a differential amplifying portion containing a first inverter coupled to a second inverter such as to form an unbalanced flip-flop circuit; a first and second bit line connected to one end of the first and second inverter, respectively; and a first and second source line connected to the other end of the first and second inverter, respectively; characterized by the register cell further comprising a first and second magnetic tunnel junction electrically connected to the other end of the first and second inverter, respectively. The shift register disclosed herein can be made smaller than conventional shift registers and power consumption during the write and read operation of the shift registers can be low. The shift register disclosed herein can be made smaller than conventional shift registers and power consumption during the write and read operation of the shift registers can be low.
    • 本发明涉及一种寄存器单元,包括:差分放大部分,其包含耦合到第二反相器的第一反相器,以形成不平衡触发器电路; 分别连接到第一和第二反相器的一端的第一和第二位线; 以及分别连接到所述第一和第二逆变器的另一端的第一和第二源极线; 其特征在于寄存器单元还包括分​​别电连接到第一和第二反相器的另一端的第一和第二磁性隧道结。 这里公开的移位寄存器可以比常规移位寄存器小,并且在移位寄存器的写入和读取操作期间的功率消耗可以是低的。 这里公开的移位寄存器可以比常规移位寄存器小,并且在移位寄存器的写入和读取操作期间的功率消耗可以是低的。