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1. 发明申请

US20120143889A1 Apparatus, System, And Method For Matching Patterns With An Ultra Fast Check Engine 有权
标题翻译：用超快速检测引擎匹配模式的装置，系统和方法
公开(公告)号：US20120143889A1
公开(公告)日：2012-06-07
申请号：US13309369
申请日：2011-12-01
申请人： Bertrand F. Cambou , Neal Berger , Mourad El Baraji
发明人： Bertrand F. Cambou , Neal Berger , Mourad El Baraji
IPC分类号： G06F17/30
CPC分类号： G06F11/08 , G06F7/02 , G06F2207/025 , G11C11/1673 , G11C11/1675 , G11C11/5607 , G11C15/02 , G11C15/046
摘要： A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.
摘要翻译：检查引擎包括多个比较器，每个比较器包括对齐以存储包括在一组参考比特中的至少一个参考比特的第一方向特性，以及对准以呈现包括在一组目标比特中的至少一个目标比特的第二方向特性。多个比较器中的每一个被配置为基于第一方向特性和第二方向特性之间的相对对准来产生表示所述至少一个目标位和所述至少一个参考位之间的匹配水平的输出。检查引擎被配置为使得多个比较器的输出被组合以产生组合输出。检查引擎被配置为基于多个比较器的组合输出来确定目标比特的集合与参考比特集匹配。

2. 发明授权

US08717794B2 Apparatus, system, and method for matching patterns with an ultra fast check engine 有权
标题翻译：用于匹配模式与超快速检查引擎的装置，系统和方法
公开(公告)号：US08717794B2
公开(公告)日：2014-05-06
申请号：US13309369
申请日：2011-12-01
申请人： Bertrand F. Cambou , Neal Berger , Mourad El Baraji
发明人： Bertrand F. Cambou , Neal Berger , Mourad El Baraji
IPC分类号： G11C15/02
CPC分类号： G06F11/08 , G06F7/02 , G06F2207/025 , G11C11/1673 , G11C11/1675 , G11C11/5607 , G11C15/02 , G11C15/046
摘要： A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.
摘要翻译：检查引擎包括多个比较器，每个比较器包括对齐以存储包括在一组参考比特中的至少一个参考比特的第一方向特性，以及对准以呈现包括在一组目标比特中的至少一个目标比特的第二方向特性。多个比较器中的每一个被配置为基于第一方向特性和第二方向特性之间的相对对准来产生表示所述至少一个目标位和所述至少一个参考位之间的匹配水平的输出。检查引擎被配置为使得多个比较器的输出被组合以产生组合输出。检查引擎被配置为基于多个比较器的组合输出来确定目标比特的集合与参考比特集匹配。

3. 发明申请

US20120143554A1 Apparatus, System, And Method For Matching Patterns With An Ultra Fast Check Engine Based On Flash Cells 有权
标题翻译：基于闪存单元的超快速检测引擎匹配模式的装置，系统和方法
公开(公告)号：US20120143554A1
公开(公告)日：2012-06-07
申请号：US13309475
申请日：2011-12-01
申请人： Bertrand F. Cambou , Neal Berger , Mourad El Baraji
发明人： Bertrand F. Cambou , Neal Berger , Mourad El Baraji
IPC分类号： G06F19/00
CPC分类号： G11C15/046 , G11C16/0483
摘要： A check engine includes a plurality of comparators, each including a plurality of flash cells, where each of the plurality of comparators is configured to store at least one reference bit included in a set of reference bits, and includes an input for presenting at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.
摘要翻译：检查引擎包括多个比较器，每个比较器包括多个闪存单元，其中多个比较器中的每一个被配置为存储包括在一组参考位中的至少一个参考位，并且包括用于呈现至少一个目标位包含在一组目标位中。多个比较器中的每一个被配置为产生表示至少一个目标位与至少一个参考位之间的匹配水平的输出。检查引擎被配置为使得多个比较器的输出被组合以产生组合输出。检查引擎被配置为基于多个比较器的组合输出来确定目标比特的集合与参考比特集匹配。

4. 发明授权

US09218879B2 Apparatus, system, and method for matching patterns with an ultra fast check engine based on flash cells 有权
标题翻译：基于闪存单元的超快速检测引擎匹配模式的装置，系统和方法
公开(公告)号：US09218879B2
公开(公告)日：2015-12-22
申请号：US13309475
申请日：2011-12-01
申请人： Bertrand F. Cambou , Neal Berger , Mourad El Baraji
发明人： Bertrand F. Cambou , Neal Berger , Mourad El Baraji
IPC分类号： G11C16/06 , G11C15/04 , G11C16/04
CPC分类号： G11C15/046 , G11C16/0483
摘要： A check engine includes comparators, where each comparator has flash cells. Each comparator is configured to store at least one reference bit included in a set of reference bits defining a first pattern. Each comparator also includes an input for presenting at least one target bit included in a set of target bits defining a second pattern. Each comparator is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit. The check engine is configured such that the outputs of the comparators are combined to produce a combined output that is compared to a reference signal to determine whether there is a match between the first pattern and the second pattern.
摘要翻译：检查引擎包括比较器，其中每个比较器具有闪存单元。每个比较器被配置为存储包括在限定第一模式的一组参考位中的至少一个参考位。每个比较器还包括用于呈现包含在定义第二图案的目标比特集合中的至少一个目标比特的输入。每个比较器被配置为产生表示所述至少一个目标位与所述至少一个参考位之间的匹配水平的输出。检查引擎被配置为使得比较器的输出被组合以产生与参考信号相比较的组合输出，以确定第一图案和第二图案之间是否存在匹配。

5. 发明申请

US20130070521A1 Magnetic Random Access Memory Devices Including Heating Straps 有权
标题翻译：包括加热带的磁性随机存取存储器件
公开(公告)号：US20130070521A1
公开(公告)日：2013-03-21
申请号：US13239168
申请日：2011-09-21
申请人： Mourad El Baraji , Neal Berger
发明人： Mourad El Baraji , Neal Berger
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/5607
摘要： A memory device includes at least one magnetic random access memory cell, which includes: (1) a magnetic tunnel junction having a first end and a second end; and (2) a strap electrically coupled to the second end of the magnetic tunnel junction. The memory device also includes a bit line electrically coupled to the first end of the magnetic tunnel junction. During a write operation, the bit line is configured to apply a first heating current through the magnetic tunnel junction, and the strap is configured to apply a second heating current through the strap, such that the magnetic tunnel junction is heated to at least a threshold temperature according to the first heating current and the second heating current.
摘要翻译：存储器件包括至少一个磁性随机存取存储器单元，其包括：（1）具有第一端和第二端的磁性隧道结; 和（2）电耦合到磁性隧道结的第二端的带子。存储器件还包括电耦合到磁性隧道结的第一端的位线。在写入操作期间，位线被配置为施加通过磁性隧道结的第一加热电流，并且带被配置为施加第二加热电流通过带，使得磁性隧道结被加热至至少阈值根据第一加热电流和第二加热电流的温度。

6. 发明申请

US20120201074A1 Magnetic Random Access Memory Devices Configured for Self-Referenced Read Operation 有权
标题翻译：配置为自参考读取操作的磁性随机存取存储器件
公开(公告)号：US20120201074A1
公开(公告)日：2012-08-09
申请号：US13023442
申请日：2011-02-08
申请人： Neal Berger , Mourad El Baraji
发明人： Neal Berger , Mourad El Baraji
IPC分类号： G11C11/00
CPC分类号： G11C11/5607 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic random access memory cell includes a sense layer, a storage layer, and a spacer layer disposed between the sense layer and the storage layer. During a write operation, the storage layer has a magnetization direction that is switchable between m directions to store data corresponding to one of m logic states, with m>2. During a read operation, the sense layer has a magnetization direction that is varied, relative to the magnetization direction of the storage layer, to determine the data stored by the storage layer.
摘要翻译：磁性随机存取存储单元包括感测层，存储层和设置在感测层和存储层之间的间隔层。在写入操作期间，存储层具有可在m个方向之间切换的磁化方向，以存储对应于m个逻辑状态之一的数据，其中m> 2。在读取操作期间，感测层具有相对于存储层的磁化方向变化的磁化方向，以确定由存储层存储的数据。

7. 发明授权

US08441844B2 Method for writing in a MRAM-based memory device with reduced power consumption 有权
标题翻译：在基于MRAM的存储器件中写入功耗降低的方法
公开(公告)号：US08441844B2
公开(公告)日：2013-05-14
申请号：US13155669
申请日：2011-06-08
申请人： Mourad El Baraji , Neal Berger
发明人： Mourad El Baraji , Neal Berger
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C11/1673 , G11C11/1675
摘要： A method of writing in a memory device comprising a plurality of MRAM cells, each cell including a magnetic tunnel junction having a resistance that can be varied during a write operation when heated at a high threshold temperature; a plurality of word lines connecting cells along a row; and a plurality of bit lines connecting cells along a column; the method comprising supplying a bit line voltage to one of the bit lines and a word line voltage to one of the word lines for passing a heating current through the magnetic tunnel junction of a selected cell; said word line voltage is a word line overdrive voltage being higher than the core operating voltage of the cells such that the heating current has a magnitude that is high enough for heating the magnetic tunnel junction at the predetermined high threshold temperature. The memory device can be written with low power consumption.
摘要翻译：一种在包括多个MRAM单元的存储器件中写入的方法，每个单元包括具有在写入操作期间可以在高阈值温度下加热时可改变的电阻的磁性隧道结; 沿着一行连接单元的多个字线; 以及沿着列连接单元的多个位线; 该方法包括向位线之一提供位线电压，并将字线电压提供给一条字线，以使加热电流通过选定单元的磁性隧道结; 所述字线电压是字线过驱动电压高于电池的核心工作电压，使得加热电流具有足够高的程度，以在预定的高阈值温度下加热磁性隧道结。可以以低功耗写入存储器件。

8. 发明申请

US20120314487A1 Magnetic Random Access Memory Devices Including Multi-Bit Cells 有权
标题翻译：包括多位单元的磁性随机存取存储器件
公开(公告)号：US20120314487A1
公开(公告)日：2012-12-13
申请号：US13158312
申请日：2011-06-10
申请人： Mourad El Baraji , Neal Berger , Lucien Lombard , Lucian Prejbeanu , Ricardo Alves Ferreira Costa E Sousa , Guillaume Prenat
发明人： Mourad El Baraji , Neal Berger , Lucien Lombard , Lucian Prejbeanu , Ricardo Alves Ferreira Costa E Sousa , Guillaume Prenat
IPC分类号： G11C11/416
CPC分类号： G11C11/5607 , G11C11/161 , G11C11/1673 , G11C11/1675
摘要： A magnetic random access memory (“MRAM”) cell includes: (1) a first magnetic layer having a first magnetization direction and a magnetic anisotropy axis; (2) a second magnetic layer having a second magnetization direction; and (3) a spacer layer disposed between the first magnetic layer and the second magnetic layer. The MRAM cell also includes a field line magnetically coupled to the MRAM cell and configured to induce a write magnetic field along a magnetic field axis, and the magnetic anisotropy axis is tilted relative to the magnetic field axis. During a write operation, the first magnetization direction is switchable between m directions to store data corresponding to one of m logic states, with m>2, at least one of the m directions is aligned relative to the magnetic anisotropy axis, and at least another one of the m directions is aligned relative to the magnetic field axis.
摘要翻译：磁性随机存取存储器（MRAM）单元包括：（1）具有第一磁化方向和磁各向异性轴的第一磁性层; （2）具有第二磁化方向的第二磁性层; 和（3）设置在第一磁性层和第二磁性层之间的间隔层。 MRAM单元还包括磁耦合到MRAM单元并且被配置为沿着磁场轴诱导写磁场的磁场线，并且磁各向异性轴相对于磁场轴倾斜。在写入操作期间，第一磁化方向可以在m个方向之间切换以存储对应于m个逻辑状态中的一个的数据，其中m≥2，m个方向中的至少一个相对于磁各向异性轴对准，并且至少另一个 m个方向中的一个相对于磁场轴线对准。

9. 发明申请

US20100302832A1 NON-VOLATILE LOGIC DEVICES USING MAGNETIC TUNNEL JUNCTIONS 有权
标题翻译：使用磁性隧道结的非易失性逻辑器件
公开(公告)号：US20100302832A1
公开(公告)日：2010-12-02
申请号：US12784848
申请日：2010-05-21
申请人： Neal Berger , Mourad El Baraji
发明人： Neal Berger , Mourad El Baraji
IPC分类号： G11C19/00
CPC分类号： G11C19/08 , G11C8/04 , G11C11/1675 , G11C14/0081 , G11C19/02
摘要： The present disclosures concerns a register cell comprising a differential amplifying portion containing a first inverter coupled to a second inverter such as to form an unbalanced flip-flop circuit; a first and second bit line connected to one end of the first and second inverter, respectively; and a first and second source line connected to the other end of the first and second inverter, respectively; characterized by the register cell further comprising a first and second magnetic tunnel junction electrically connected to the other end of the first and second inverter, respectively. The shift register disclosed herein can be made smaller than conventional shift registers and power consumption during the write and read operation of the shift registers can be low. The shift register disclosed herein can be made smaller than conventional shift registers and power consumption during the write and read operation of the shift registers can be low.
摘要翻译：本发明涉及一种寄存器单元，包括：差分放大部分，其包含耦合到第二反相器的第一反相器，以形成不平衡触发器电路; 分别连接到第一和第二反相器的一端的第一和第二位线; 以及分别连接到所述第一和第二逆变器的另一端的第一和第二源极线; 其特征在于寄存器单元还包括分别电连接到第一和第二反相器的另一端的第一和第二磁性隧道结。这里公开的移位寄存器可以比常规移位寄存器小，并且在移位寄存器的写入和读取操作期间的功率消耗可以是低的。这里公开的移位寄存器可以比常规移位寄存器小，并且在移位寄存器的写入和读取操作期间的功率消耗可以是低的。

10. 发明授权

US08625336B2 Memory devices with series-interconnected magnetic random access memory cells 有权
标题翻译：具有串联互连磁存储单元的存储器件
公开(公告)号：US08625336B2
公开(公告)日：2014-01-07
申请号：US13023441
申请日：2011-02-08
申请人： Neal Berger , Mourad El Baraji
发明人： Neal Berger , Mourad El Baraji
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659 , G11C11/1673
摘要： A memory device includes magnetic random access memory (“MRAM”) cells that are electrically connected in series, each one of the MRAM cells having a storage magnetization direction and a sense magnetization direction. During a write operation, multiple ones of the MRAM cells are written in parallel by switching the storage magnetization directions of the MRAM cells. During a read operation, a particular one of the MRAM cells is read by varying the sense magnetization direction of the particular one of the MRAM cells, relative to the storage magnetization direction of the particular one of the MRAM cells.
摘要翻译：存储器件包括串联电连接的磁随机存取存储器（“MRAM”）单元，每个MRAM单元具有存储磁化方向和感测磁化方向。在写入操作期间，通过切换MRAM单元的存储磁化方向来并行写入多个MRAM单元。在读取操作期间，通过相对于特定MRAM单元的存储磁化方向改变特定MRAM单元的感测磁化方向来读取特定的一个MRAM单元。

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