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1. 发明授权

US5061925A Phase equalization system for a digital-to-analog converter utilizing separate digital and analog sections 失效
标题翻译：使用单独的数字和模拟部分的数模转换器的相位均衡系统
公开(公告)号：US5061925A
公开(公告)日：1991-10-29
申请号：US571376
申请日：1990-08-22
申请人： Navdeep S. Sooch , Donald A. Kerth , Eric J. Swanson , Tetsurou Sugimoto
发明人： Navdeep S. Sooch , Donald A. Kerth , Eric J. Swanson , Tetsurou Sugimoto
IPC分类号： H03M1/66 , H03H17/00 , H03H17/02 , H03H17/06 , H03M3/02 , H03M7/00 , H03M7/32
CPC分类号： H03M3/37 , H03M3/50 , H03M7/3028 , H03M7/3035 , H03M7/3037
摘要： A phase equalization system for a digital-to-analog converter (DAC) includes a digital portion (10) having an interpolation section (14) for receiving a digital input and increasing the sampling frequency thereof for input to a delta-sigma modulator (16). A summing junction (24) is disposed between the interpolation circuit (14) and the delta-sigma modudlator (16) to allow an offset voltage to be summed therewith. This provides for D.C. offset, this offset being controlled by a calibration control (40). The output of the digital section (10) is input in an analog section (12), which has a one-bit DAC 21) that is input to an analog filter (22) for converting and filtering the one-bit digital stream output by the delta-sigma modulator (16). The interpolation circuit (14) includes a three stage interpolation filter comprising a first stage (50), a second stage (52) and a third stage (54). The second stage (52) is comprised of a finite impulse response filter (FIR) that has a nonlinear phase response. The nonlinear phase response of the interpolation filter (52) compensates for the phase deviation of the analog filter (22) from a linear phase response. Therefore, the composite phase provided by the combination of the phase equalization in the digital section (10) and the phase nonlinearity in the analog section (12) will result in a linear overall phase relationship for the DAC.
摘要翻译：用于数模转换器（DAC）的相位均衡系统包括具有插值部分（14）的数字部分（10），用于接收数字输入并增加其采样频率以输入到Δ-Σ调制器（16 ）。在插值电路（14）和Δ-Σ调制器（16）之间设置加法结（24），以允许偏移电压与其相加。这提供直流偏移，该偏移由校准控制（40）控制。数字部分（10）的输出被输入到模拟部分（12）中，模拟部分（12）具有一个比特DAC21），该模拟部分（12）被输入到模拟滤波器（22），用于转换和滤波由 Δ-Σ调制器（16）。内插电路（14）包括三级内插滤波器，包括第一级（50），第二级（52）和第三级（54）。第二级（52）由具有非线性相位响应的有限脉冲响应滤波器（FIR）组成。内插滤波器（52）的非线性相位响应补偿模拟滤波器（22）与线性相位响应的相位偏差。因此，通过数字部分（10）中的相位均衡和模拟部分（12）中的相位非线性的组合提供的复合相位将导致DAC的线性整体相位关系。

2. 发明授权

US5079550A Combining continuous time and discrete time signal processing in a delta-sigma modulator 失效
标题翻译：在Δ-Σ调制器中组合连续时间和离散时间信号处理
公开(公告)号：US5079550A
公开(公告)日：1992-01-07
申请号：US428396
申请日：1989-10-27
申请人： Navdeep S. Sooch , Donald A. Kerth , Bruce P. Del Signore , Eric J. Swanson
发明人： Navdeep S. Sooch , Donald A. Kerth , Bruce P. Del Signore , Eric J. Swanson
IPC分类号： H03M3/02
CPC分类号： H03M3/496 , H03M3/43 , H03M3/438
摘要： An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which operates as a continuous time integrator. the second, third, and fourth integrator stages are discrete time or sampling integrators. The continuous time first integrator provides the required thermal noise characteristics of the loop filter while the discrete time integrator stages provide loop stability and transfer characteristics which are advantageous to the overall operation of the analog-to-digital modulator.
摘要翻译：过采样模数转换器包括具有作为连续时间积分器工作的第一积分器级的模拟环路滤波器。第二，第三和第四积分器级是离散时间或采样积分器。连续时间第一积分器提供环路滤波器所需的热噪声特性，而离散时间积分器级提供有利于模数转换器的整体运行的环路稳定性和传输特性。

3. 发明授权

US4746899A Method for reducing effects of electrical noise in an analog-to-digital converter 失效
标题翻译：降低模数转换器电噪声影响的方法
公开(公告)号：US4746899A
公开(公告)日：1988-05-24
申请号：US916160
申请日：1986-10-07
申请人： Eric J. Swanson , Navdeep S. Sooch , David J. Knapp
发明人： Eric J. Swanson , Navdeep S. Sooch , David J. Knapp
IPC分类号： H03M1/08 , H03M3/02
CPC分类号： H03M3/324 , H03M3/458
摘要： Method for reducing deleterious effects of electrical noise in an analog-to-digital converter wherein both the analog and digital circuitry of the A/D converter are embodied in the same integrated circuit. The method includes sampling an analog input voltage with a first clock signal, generating a second clock signal that is delayed with respect to the first clock signal, and using the second clock signal as a clock for the digital circuitry. In accordance with another aspect of the invention, the method for reducing effects of noise in an A/D converter wherein such noise is generated by a digital decimation filter includes synchronously pipelining the arithmetic operations of the digital decimation filter.
摘要翻译：用于减少模数转换器中电噪声的有害影响的方法，其中A / D转换器的模拟和数字电路都体现在相同的集成电路中。该方法包括用第一时钟信号对模拟输入电压进行采样，产生相对于第一时钟信号被延迟的第二时钟信号，并且使用第二时钟信号作为数字电路的时钟。根据本发明的另一方面，用于减少A / D转换器中的噪声影响的方法，其中这种噪声由数字抽取滤波器产生，包括同步流水线数字抽取滤波器的算术运算。

4. 发明授权

US5644257A Sampling circuit charge management 失效
标题翻译：采样电路充电管理
公开(公告)号：US5644257A
公开(公告)日：1997-07-01
申请号：US635570
申请日：1996-04-22
申请人： Donald A. Kerth , Dan B. Kasha , Eric J. Swanson , Anthony G. Mellissinos
发明人： Donald A. Kerth , Dan B. Kasha , Eric J. Swanson , Anthony G. Mellissinos
IPC分类号： G06G7/14 , G11C27/02 , H03K5/24 , H03K5/159 , G06G7/10
CPC分类号： G11C27/024 , G06G7/14 , G11C27/02 , H03K5/2481 , H03K5/249
摘要： The detrimental nonlinear charging currents from an analog input signal through an anti-aliasing filter into a sampling circuit can be minimized by using primary and secondary inputs to the sampling circuit. The secondary input is turned on before the primary input and the charge required to charge the parasitic capacitance inside the sampling circuit and to replenish the channeling charge lost in the previous cycle is supplied primarily through the secondary input. Immediately after the secondary input is turned off the primary input is connected to the sampling node, and only the charge required to fine tune the signal into the sampling capacitor is drawn through the primary input. Therefore, most of the non-linear charge injection is passed through the secondary input, and the signal passed through the primary input is used to fine tune the voltage levels inside the sampling circuit during the actual sampling operation.
摘要翻译：通过使用初级和次级输入到采样电路，可以将模拟输入信号通过抗混叠滤波器到采样电路的有害非线性充电电流最小化。辅助输入在主输入之前被接通，并且为采样电路内的寄生电容充电所需的电荷和补充前一周期中丢失的通道电荷主要通过次级输入提供。在二次输入关闭之后，主输入端立即连接到采样节点，只有通过主输入才能将信号微调到采样电容器中所需的电荷。因此，大多数非线性电荷注入通过二次输入，并且通过主输入的信号用于在实际采样操作期间微调采样电路内部的电压电平。

5. 发明授权

US5621339A Method and apparatus for removing trapped oxide charge from a differential input stage 失效
标题翻译：用于从差分输入级去除捕获的氧化物电荷的方法和装置
公开(公告)号：US5621339A
公开(公告)日：1997-04-15
申请号：US121244
申请日：1993-09-14
申请人： Donald A. Kerth , Eric J. Swanson
发明人： Donald A. Kerth , Eric J. Swanson
IPC分类号： H03F3/45 , H03K5/24 , H03K5/22
CPC分类号： H03F3/45479 , H03K5/2481 , H03K5/249 , H03F2200/331
摘要： A differential input stage for a data conversion device includes two sections, one section for operating during a high stress portion of a charge transfer operation and one portion for operating during the remainder of the charge transfer operation. The first portion is comprised of two differential transistors (84) and (86) having the sources and bodies thereof connected to a source coupled node and connected through a switch (94) to a current source (92). The drains of transistors (84) and (86) are connected through switches (110) and (112), respectively, to output terminals. During the second half of the charge transfer operation, differential transistors (78) and (88), having the sources and bodies thereof connected to a source coupled node and connected to the current source (92) through a switch (90), are rendered operable with the drains thereof connected through switches (96) and (104), respectively, to the output terminals. Only one of the differential pairs is operable at any one time. When they are not operational, the sources, bodies and drains thereof are connected together and to a flush terminal (118) through respective switches. These switches flush out trapped oxide charges and allow the charges to once again become mobile.
摘要翻译：用于数据转换装置的差分输入级包括两个部分，一个部分用于在电荷转移操作的高应力部分期间操作，一个部分用于在剩余的电荷转移操作期间操作。第一部分包括两个差分晶体管（84）和（86），它们的源极和本体连接到源极耦合节点，并通过开关（94）连接到电流源（92）。晶体管（84）和（86）的漏极分别通过开关（110）和（112）连接到输出端子。在电荷转移操作的第二半期间，具有连接到源耦合节点并且通过开关（90）连接到电流源（92）的源极和主体的差分晶体管（78）和（88）被渲染可操作地将其通过开关（96）和（104）连接的排水口分别连接到输出端子。差分对只有一个可以在任何一个时间工作。当它们不可操作时，其源极，主体和下水道通过相应的开关连接在一起并连接到冲水端子（118）。这些开关清除被捕获的氧化物电荷，并允许电荷再次移动。

6. 发明授权

US5012244A Delta-sigma modulator with oscillation detect and reset circuit 失效
标题翻译：具有振荡检测和复位电路的Δ-Σ调制器
公开(公告)号：US5012244A
公开(公告)日：1991-04-30
申请号：US429214
申请日：1989-10-27
申请人： David R. Wellard , Donald A. Kerth , Bruce P. Del Signore , Eric J. Swanson
发明人： David R. Wellard , Donald A. Kerth , Bruce P. Del Signore , Eric J. Swanson
IPC分类号： H03M3/02
CPC分类号： H03M3/364 , H03M3/43 , H03M3/448 , H03M3/452
摘要： An oscillation detect and reset circuit is provided for an analog modulator that includes a first stage of integration having a single ended differential amplifier (32) which is connected to the input of three stages of subsequent integration (40), (42) and (44), in a cascaded configuration. The output of the last stage of integration (44) is connected to the input of a one-bit quantizer (48). The output of the one-bit quantizer (48) is connected to the input of a current (50) feedback, which is connected between a summing node (36) and a negative voltage supply. The summing node (36) sums the current feedback with an input voltage for input to the amplifier (32). Switches (52), (54) and (56) are provided across the inputs and outputs of the integration stages (40), (42) and (44), respectively. The sensing of an unstable condition on the output of second stage of integration (40) is detected by oscillation detect comparators (60) and (62) to initiate a count cycle in a five-bit counter (66). The output of counter (66) generates a oscillation detect signal upon detection of an oscillation, which signal is output to the control inputs of the switches (52), (54) and (56), for thirty-two cycles of the analog modulator sampling frequency. This is a sufficient amount of time to allow the loop, which is a first order loop, to zero out during the reset period.
摘要翻译：提供了一种用于模拟调制器的振荡检测和复位电路，该模拟调制器包括具有单端差分放大器（32）的第一级积分，该单端差分放大器连接到三级后续积分（40），（42）和（44 ），在级联配置中。最后一级积分（44）的输出端连接到一位量化器（48）的输入端。一比特量化器（48）的输出连接到连接在求和节点（36）和负电压源之间的电流（50）反馈的输入。求和节点（36）将电流反馈与用于输入到放大器（32）的输入电压相加。分别在积分级（40），（42）和（44）的输入和输出两端提供开关（52），（54）和（56）。通过振荡检测比较器（60）和（62）检测第二级积分（40）输出的不稳定状态，以启动五位计数器（66）中的计数周期。计数器（66）的输出在检测到振荡时产生振荡检测信号，该信号在模拟调制器（52），（54）和（56）的控制输入端输出三十二个周期采样频率。这是足够的时间来允许在复位周期期间循环（这是第一阶循环）为零。

7. 发明授权

US08093951B1 Pulse-width modulated (PWM) audio power amplifier having output signal magnitude controlled pulse voltage and switching frequency 有权
标题翻译：脉冲宽度调制（PWM）音频功率放大器具有输出信号幅值受控的脉冲电压和开关频率
公开(公告)号：US08093951B1
公开(公告)日：2012-01-10
申请号：US12568667
申请日：2009-09-28
申请人： Lingli Zhang , Dan Shen , Johann Gaboriau , Eric J. Swanson
发明人： Lingli Zhang , Dan Shen , Johann Gaboriau , Eric J. Swanson
IPC分类号： H03F3/217 , H03F3/04
CPC分类号： H03F3/217 , H03F2200/03 , H03F2200/114 , H03F2200/351
摘要： An audio switching power amplifier having an output pulse voltage selected in conformity with an indication of the output signal amplitude provides lower electromagnetic interference (EMI) in class-D amplifier implementations, in particular, in inductor-less designs. The output pulse voltage may be selected by providing multiple switching circuits, such as half or fully bridge switches, with each switching circuit connected to a different power supply. One of the switching circuits is activated by the switching controller, while the others are disabled, providing selection of the output pulse voltage. Selection of a lower pulse voltage, when the maximum voltage is not required, reduces the generated EMI. The switching frequency of the class-D amplifier may also be controlled in conformity with the output signal amplitude, so that at higher output levels a lower switching rate is selected, reducing the generated EMI.
摘要翻译：具有根据输出信号幅度的指示选择的输出脉冲电压的音频开关功率放大器在D类放大器实现中尤其是在无电感设计中提供较低的电磁干扰（EMI）。可以通过提供多个开关电路（例如半桥或全桥开关）来选择输出脉冲电压，每个开关电路连接到不同的电源。其中一个开关电路由开关控制器激活，而其他开关电路被禁用，提供输出脉冲电压的选择。当不需要最大电压时，选择较低的脉冲电压可以减少产生的EMI。 D类放大器的开关频率也可以根据输出信号幅度进行控制，从而在较高的输出电平下选择较低的开关速率，从而减少产生的EMI。

8. 发明授权

US06901423B1 Noise invariant circuits, systems and methods 有权
公开(公告)号：US06901423B1
公开(公告)日：2005-05-31
申请号：US09840530
申请日：2001-04-23
申请人： Edwin De Angel , Eric J. Swanson
发明人： Edwin De Angel , Eric J. Swanson
IPC分类号： G06F1/26 , G06F7/52 , G06F7/533 , G06J1/00
CPC分类号： G06F7/5336 , G06F2207/3868
摘要： The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a low-power mode of operation. A noise invariant circuit disables row skip operation in a multi-row multiplier, to enable analog sampling. Disabling of the row skip operation is accomplished at a time which is several digital cycles preceding the time of analog sampling. Power saving multiplier row skippage resumes after analog sampling is completed.

9. 发明授权

US06590517B1 Analog to digital conversion circuitry including backup conversion circuitry 失效
标题翻译：模数转换电路包括备用转换电路
公开(公告)号：US06590517B1
公开(公告)日：2003-07-08
申请号：US10061791
申请日：2002-02-01
申请人： Eric J. Swanson
发明人： Eric J. Swanson
IPC分类号： H03M112
CPC分类号： H03M1/187 , H03M1/185 , H03M1/208
摘要： An autoranging analog to digital conversion system is provided. The system may include a digitally programmable preamplifier for amplifying a difference between an analog input and an estimate of the analog input. The preamplifier may be coupled to an analog to digital converter for converting the preamplifier output to a digital signal. The system may also include digital domain predictor or estimation logic for determining an optimum gain and analog input estimate for a given analog input. Multiple signal input channels may be coupled to the analog to digital conversion system. The autoranging estimations may be performed on a sample by sample basis or a channel by channel basis. The conversion system may also include the use of a backup conversion path for use when the main conversion path overranges. The backup conversion path may utilize a dedicated backup converter. The backup conversion path may alternatively utilize the estimation converter to generate backup conversions or may utilize the main converter to generate backup conversions.
摘要翻译：提供了一种自动量程模数转换系统。该系统可以包括用于放大模拟输入和模拟输入的估计之间的差的数字可编程前置放大器。前置放大器可以耦合到模数转换器，用于将前置放大器输出转换成数字信号。该系统还可以包括用于确定给定模拟输入的最佳增益和模拟输入估计的数字域预测器或估计逻辑。多个信号输入通道可以耦合到模数转换系统。自动量程估计可以根据样本或逐个频道进行。转换系统还可以包括使用备用转换路径，以便在主转换路径超出时使用。备用转换路径可以利用专用备用转换器。备选转换路径可以替代地使用估计转换器来产生备份转换，或者可以利用主转换器来生成备份转换。

10. 发明授权

US06356872B1 Method and apparatus for storing digital audio and playback thereof 失效
标题翻译：用于存储数字音频及其回放的方法和装置
公开(公告)号：US06356872B1
公开(公告)日：2002-03-12
申请号：US08719986
申请日：1996-09-25
申请人： Ka Yin Leung , Eric J. Swanson , Kafai Leung
发明人： Ka Yin Leung , Eric J. Swanson , Kafai Leung
IPC分类号： G10L2100
CPC分类号： G10L21/0364
摘要： A data conversion device is provided for storing digital data in a DAT (332) at a 16-bit word length and then recovering the data at a 24-bit word length with an overall reduction in truncation noise that would be inherently associated with data at the 16-bit word length. This is facilitated by noise shaping the data at the 16-bit word length prior to storage in the DAT (332) with a noise-shaping filter (324). This results in truncation noise in the lower portion of the frequency band being shifted to the higher portion of the band. When the data is recovered, it is converted to a 24-bit word length and then processed through a bandpass filter to filter out the higher frequency noise to yield a signal that has a maximum noise equal to or less than that in the lower portion of the band stored in the DAT (332). Since the truncation noise was shifted from the lower band to the upper band, this is a lower noise level than that inherently associated with the 16-bit word length.
摘要翻译：提供了一种数据转换装置，用于以16位字长将数字数据存储在DAT（332）中，然后以24位字长恢复数据，同时全局减少截断噪声，该截断噪声本质上与 16位字长。这通过在使用噪声整形滤波器（324）存储在DAT（332）中之前对16位字长的数据进行噪声整形来促进。这导致频带下部的截断噪声转移到频带的较高部分。当数据被恢复时，将其转换为24位字长，然后通过带通滤波器进行处理，以滤除更高频率的噪声，以产生最大噪声等于或小于存储在DAT（332）中的乐队。由于截断噪声从较低频带偏移到较高频带，因此与16位字长固有相关的噪声水平较低。

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