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1. 发明授权

US5428235A Semiconductor memory device including improved connection structure to FET elements 失效
标题翻译：半导体存储器件包括改进的与FET元件的连接结构
公开(公告)号：US5428235A
公开(公告)日：1995-06-27
申请号：US300878
申请日：1994-09-06
申请人： Masahiro Shimizu , Takehisa Yamaguchi , Natsuo Ajika
发明人： Masahiro Shimizu , Takehisa Yamaguchi , Natsuo Ajika
IPC分类号： H01L27/108 , H01L29/68
CPC分类号： H01L27/10808
摘要： A memory cell of a DRAM comprises one MOS transistor and one capacitor. The MOS transistor includes a pair of source/drain regions and a gate electrode formed on the channel region. A bit line is formed so as to be connected to the source/drain region. A conductive layer is formed so as to be connected to the source/drain region. The gate electrode includes a first part formed on the channel region with an oxide film interposedand second and third parts extending from the first part, respectively, and formed on the bit line and the conductive layer with an interlayer oxide film interposed. The capacitor includes a lower electrode formed so as to be connected to the conductive layer and an upper electrode formed so as to be opposed to the surface of the lower electrode with a dielectric film interposed. The upper electrode is placed above the bit line. A word line is placed above the upper electrode and connected to the gate electrode. It is possible to provide a field effect transistor in which increase in speed can be realized and to provide a semiconductor memory device in which capacitance of the capacitor can be sufficiently secured in case of making miniaturization of the memory cell. It is also possible to prevent decrease in reliability caused by disconnection of the bit line.
摘要翻译： DRAM的存储单元包括一个MOS晶体管和一个电容器。 MOS晶体管包括一对源极/漏极区域和形成在沟道区域上的栅极电极。形成位线以便连接到源极/漏极区域。导电层形成为连接到源/漏区。栅电极包括形成在沟道区上的第一部分，其中介于氧化膜之间，第二和第三部分分别从第一部分延伸并且形成在位线上，并且导电层被插入夹层氧化膜。电容器包括形成为连接到导电层的下电极和形成为与介电膜插入的下电极的表面相对的上电极。上电极位于位线上方。字线放置在上电极上方并连接到栅电极。可以提供一种可以实现速度增加的场效应晶体管，并且提供一种在使存储单元小型化的情况下能够充分确保电容器的电容的半导体存储器件。也可以防止由位线的断线引起的可靠性降低。

2. 发明授权

US5347151A DRAM with memory cells having access transistor formed on solid phase epitaxial single crystalline layer and manufacturing method thereof 失效
标题翻译：具有在固相外延单晶层上形成的存取晶体管的存储单元的DRAM及其制造方法
公开(公告)号：US5347151A
公开(公告)日：1994-09-13
申请号：US797888
申请日：1991-11-26
申请人： Masahiro Shimizu , Takehisa Yamaguchi , Natsuo Ajika
发明人： Masahiro Shimizu , Takehisa Yamaguchi , Natsuo Ajika
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L23/00
CPC分类号： H01L27/10808
摘要： Access transistors of memory cells in a DRAM are formed in a solid phrase epitaxial single crystalline layer on the surface of a silicon substrate. A bit line extending over the surface of an element isolation and insulation film is formed by patterning a polycrystalline silicon layer extending to the single crystalline silicon layer as a layer. A stacked capacitor is connected to one source/drain of the access transistor through a conductive layer extending to the single crystalline silicon layer and over a field oxide film. Part of the stacked capacitor extends over the bit line. The connection region of the bit line, the capacitor and the source/drain is formed above the element isolation and insulation film, so that the source/drain region of the access transistor can be reduced.
摘要翻译： DRAM中的存储单元的存取晶体管形成在硅衬底的表面上的固体短边外延单晶层中。在元件隔离和绝缘膜的表面上延伸的位线是通过将延伸到单晶硅层的多晶硅层图案化为一层而形成的。叠层电容器通过延伸到单晶硅层和场氧化物膜上的导电层连接到存取晶体管的一个源极/漏极。堆叠电容器的一部分在位线上延伸。位线，电容器和源极/漏极的连接区域形成在元件隔离和绝缘膜上方，从而可以减小存取晶体管的源极/漏极区域。

3. 发明授权

US5275629A Semiconductor device manufacturing apparatus 失效
标题翻译：半导体装置制造装置
公开(公告)号：US5275629A
公开(公告)日：1994-01-04
申请号：US762355
申请日：1991-09-19
申请人： Natsuo Ajika , Masahiro Shimizu , Takehisa Yamaguchi
发明人： Natsuo Ajika , Masahiro Shimizu , Takehisa Yamaguchi
IPC分类号： G01J1/28 , C23C16/48 , H01L21/00 , H01L21/205 , H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/31 , H01L21/66 , C23C16/00
CPC分类号： H01L21/67115 , C23C16/481 , Y10T29/41
摘要： A semiconductor device manufacturing apparatus has a first space and a second space in a process chamber in which a semiconductor wafer is accommodated, the first and second spaces being separated by the semiconductor wafer. A process gas port opens into the first space adjacent to the obverse surface of the semiconductor wafer, and an infrared light transmission window is formed in a wall of the chamber at the second space facing the reverse surface of the semiconductor wafer. No layers are deposited on the reverse surface of the semiconductor wafer and the infrared light transmission window so that the emissivity at the reverse surface of the semiconductor wafer is not changed during layer deposition. The temperature during processing can therefore be monitored accurately with a pyrometer, and a reduction in the transmissivity of the window is prevented.
摘要翻译：半导体器件制造装置在其中容纳有半导体晶片的处理室中具有第一空间和第二空间，第一和第二空间被半导体晶片隔开。处理气体通道向与半导体晶片的正面相邻的第一空间开口，并且在面向半导体晶片的背面的第二空间处，在室的壁上形成红外光透射窗。在半导体晶片和红外光透射窗的反面上没有层沉积，使得在层沉积期间半导体晶片的反面的发射率不变。因此，可以用高温计精确地监测加工过程中的温度，并且防止窗口的透射率的降低。

4. 发明授权

US08044498B2 Interposer, semiconductor chip mounted sub-board, and semiconductor package 有权
标题翻译：内插器，半导体芯片安装子板和半导体封装
公开(公告)号：US08044498B2
公开(公告)日：2011-10-25
申请号：US12164503
申请日：2008-06-30
申请人： Moriyoshi Nakashima , Kazuo Kobayashi , Natsuo Ajika
发明人： Moriyoshi Nakashima , Kazuo Kobayashi , Natsuo Ajika
IPC分类号： H01L23/07
CPC分类号： H01L25/0657 , H01L2224/48145 , H01L2224/48227 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2225/06575 , H01L2225/06596 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00012
摘要： A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on.Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.
摘要翻译：可以制造具有高无缺陷率的半导体器件，使得可以在配置其上安装有多个半导体芯片的一个封装的半导体器件时容易地保证半导体芯片的KGD（已知好裸芯片）。使得每个半导体芯片可以在终端位置，间距，信号布置等方面没有限制。提供给半导体芯片安装的密封子板的突起附接到封装基板。多个半导体裸芯片设置在形成在半导体芯片安装密封子板和封装基板之间的空间中，使得布线成为可能。

5. 发明申请

US20090175083A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090175083A1
公开(公告)日：2009-07-09
申请号：US11684035
申请日：2007-03-09
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3436
摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.
摘要翻译：非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

6. 发明授权

US06867455B2 Semiconductor device with a metal insulator semiconductor transistor 失效
标题翻译：具有金属绝缘体半导体晶体管的半导体器件
公开(公告)号：US06867455B2
公开(公告)日：2005-03-15
申请号：US10600344
申请日：2003-06-23
申请人： Yasuyoshi Itoh , Shuuichi Ueno , Haruo Furuta , Natsuo Ajika
发明人： Yasuyoshi Itoh , Shuuichi Ueno , Haruo Furuta , Natsuo Ajika
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L29/66833 , H01L21/26586 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42352 , H01L29/42368 , H01L29/513 , H01L29/66545 , H01L29/66583 , H01L29/7833 , H01L29/7923
摘要： A semiconductor device capable of holding multibit information in one memory cell, and a method of manufacturing the semiconductor device. A trench is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film of a gate insulating film which interpose the trench are caused to function as first and second electric charge holding portions capable of holding electric charges. In the case in which first electric charges are trapped on the drain side and second electric charges are trapped on the source side, a portion of a gate electrode in the trench functions as a shield. If a fixed potential is given to the gate electrode, the second electric charge holding portion is not influenced by an electric field induced by the first electric charges so that the trapping of the second electric charges is not inhibited.
摘要翻译：一种能够将多位信息保持在一个存储单元中的半导体器件，以及半导体器件的制造方法。在MONOS晶体管的沟道部分中形成沟槽。然后，使介入沟槽的栅极绝缘膜的氮化硅膜中的源极侧部分和漏极侧部分作为能够保持电荷的第一和第二电荷保持部分起作用。在第一电荷被捕获在漏极侧并且第二电荷被捕获在源极侧的情况下，沟槽中的栅电极的一部分用作屏蔽。如果向栅电极施加固定电位，则第二电荷保持部不受第一电荷引起的电场的影响，从而不抑制第二电荷的捕获。

7. 发明授权

US06441426B1 Nonvolatile semiconductor memory device and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06441426B1
公开(公告)日：2002-08-27
申请号：US09333687
申请日：1999-06-16
申请人： Atsushi Fukumoto , Natsuo Ajika
发明人： Atsushi Fukumoto , Natsuo Ajika
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7883 , Y10S257/90
摘要： In a semiconductor substrate surface, first and second trenches extending in parallel with each other in a bit line direction are provided. An insulation film for trench isolation is filled in the first and second trenches. A floating gate is provided between the first and second trenches on the semiconductor substrate. A sidewall spacer is provided on a sidewall surface, extending in the bit line direction, of the floating gate.
摘要翻译：在半导体衬底表面中，提供沿位线方向彼此平行延伸的第一和第二沟槽。用于沟槽隔离的绝缘膜填充在第一和第二沟槽中。浮置栅极设置在半导体衬底上的第一和第二沟槽之间。侧壁间隔件设置在浮动栅极的位线方向上延伸的侧壁表面上。

8. 发明授权

US6014328A Memory cell allowing write and erase with low voltage power supply and nonvolatile semiconductor memory device provided with the same 失效
标题翻译：存储单元允许使用低电压电源写入和擦除以及提供该存储器的非易失性半导体存储器件
公开(公告)号：US6014328A
公开(公告)日：2000-01-11
申请号：US35786
申请日：1998-03-06
申请人： Takahiro Onakado , Natsuo Ajika
发明人： Takahiro Onakado , Natsuo Ajika
IPC分类号： G11C16/04 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517 , G11C16/0433 , H01L27/115
摘要： In a nonvolatile semiconductor memory device, a memory cell array includes memory cell transistors and cell select transistors corresponding to the memory cell transistors, respectively. A memory cell SG decoder supplies a potential to a cell select line corresponding to the selected row. The cell select transistor opens and closes a conduction path of a current flowing between a bit line and a source line through the memory cell transistor in accordance with the potential on the cell select line. As a result, an influence by a leak current flowing from the unselected memory cell transistor in a read operation is suppressed.
摘要翻译：在非易失性半导体存储器件中，存储单元阵列分别包括与存储单元晶体管对应的存储单元晶体管和单元选择晶体管。存储单元SG解码器向对应于所选行的单元选择线提供电位。电池选择晶体管根据电池选择线上的电位来打开和闭合通过存储单元晶体管在位线和源极线之间流动的电流的导通路径。结果，抑制了在读取操作中从未选择的存储单元晶体管流过的漏电流的影响。

9. 发明授权

US5898606A Electrically programmable and erasable nonvolatile semiconductor memory device and operating method therefor 失效
标题翻译：电可编程和可擦除的非易失性半导体存储器件及其操作方法
公开(公告)号：US5898606A
公开(公告)日：1999-04-27
申请号：US841372
申请日：1997-04-30
申请人： Shinichi Kobayashi , Yasushi Terada , Yoshikazu Miyawaki , Takeshi Nakayama , Tomoshi Futatsuya , Natsuo Ajika , Yuichi Kunori , Hiroshi Onoda , Atsushi Fukumoto , Makoto Ohi
发明人： Shinichi Kobayashi , Yasushi Terada , Yoshikazu Miyawaki , Takeshi Nakayama , Tomoshi Futatsuya , Natsuo Ajika , Yuichi Kunori , Hiroshi Onoda , Atsushi Fukumoto , Makoto Ohi
IPC分类号： G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , G11C7/00
CPC分类号： H01L27/11517 , G11C16/0408 , G11C16/0416 , G11C16/16 , H01L27/105 , H01L27/115 , H01L27/11546 , H01L29/7883
摘要： In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.
摘要翻译：在擦除时，电子同时从多个存储单元的源中注入到浮动栅极中。因此，多个存储单元的阈值电压增加。在编程中，电子从所选择的存储单元的浮动栅极发射到漏极。因此，所选存储单元的阈值电压降低。

10. 发明授权

US5446301A Semiconductor device including semiconductor layer having impurity region and method of manufacturing the same 失效
标题翻译：包括具有杂质区域的半导体层的半导体器件及其制造方法
公开(公告)号：US5446301A
公开(公告)日：1995-08-29
申请号：US274517
申请日：1994-07-13
申请人： Koji Eguchi , Natsuo Ajika , Kazuyuki Sugahara
发明人： Koji Eguchi , Natsuo Ajika , Kazuyuki Sugahara
IPC分类号： H01L21/20 , H01L21/336 , H01L21/768 , H01L21/84 , H01L27/06 , H01L27/12 , H01L29/49 , H01L29/78 , H01L29/786 , H01L27/01 , H01L29/06
CPC分类号： H01L29/66772 , H01L27/0688 , H01L27/1203 , H01L29/4908 , H01L29/78654
摘要： A semiconductor device capable of effectively preventing a dielectric breakdown of a gate oxide film without adversely affecting the characteristics of a transistor and a process of manufacturing the same are disclosed. The semiconductor device comprises a SOI film 2 whose upper angular parts are rounded off by sputter etching and a gate oxide film 3 formed on SOI film 2 with an almost uniform thickness. Therefore, electric field concentration in the upper angular parts of SOI film 2 is reduced. Furthermore, the control characteristics of the transistor are enhanced by the uniform gate oxide film 3. As a result, a dielectric breakdown of the gate oxide film is effectively prevented without adversely affecting the characteristics of the transistor. Sputter etching enabling processing at a low temperature is used, so that the upper angular parts of SOI film 2 are rounded off without adversely affecting a semiconductor element formed in the lower layer.
摘要翻译：公开了能够有效地防止栅极氧化膜的介电击穿而不会不利地影响晶体管的特性的半导体器件及其制造方法。该半导体器件包括通过溅射蚀刻使上角部分被倒圆的SOI膜2和形成在具有几乎均匀厚度的SOI膜2上的栅极氧化膜3。因此，SOI膜2的上角部的电场浓度降低。此外，通过均匀的栅极氧化膜3增强晶体管的控制特性。结果，有效地防止了栅极氧化膜的电介质击穿，而不会不利地影响晶体管的特性。使用能够在低温下进行的溅射蚀刻，使得SOI膜2的上角部分被倒圆而不会对形成在下层中的半导体元件产生不利影响。

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