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1. 发明授权

US08017994B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08017994B2
公开(公告)日：2011-09-13
申请号：US12499220
申请日：2009-07-08
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
IPC分类号： H01L29/792
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译：通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

2. 发明申请

US20090310409A1 Nonvolatile Semiconductor Memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20090310409A1
公开(公告)日：2009-12-17
申请号：US12499220
申请日：2009-07-08
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
IPC分类号： G11C16/04 , H01L29/792 , G11C16/06
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译：通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

3. 发明申请

US20090065922A1 SEMICONDUCTOR DEVICE PACKAGE STRUCTURE 有权
标题翻译：半导体器件封装结构
公开(公告)号：US20090065922A1
公开(公告)日：2009-03-12
申请号：US12235734
申请日：2008-09-23
申请人： Moriyoshi NAKASHIMA , Kazuo Kobayashi , Natsuo Ajika
发明人： Moriyoshi NAKASHIMA , Kazuo Kobayashi , Natsuo Ajika
IPC分类号： H01L23/02
CPC分类号： H01L23/3135 , H01L23/3128 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/0657 , H01L2224/05554 , H01L2224/32145 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2225/0651 , H01L2225/06513 , H01L2225/0652 , H01L2225/06572 , H01L2225/06582 , H01L2225/06596 , H01L2924/00014 , H01L2924/01004 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11′). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.
摘要翻译：半导体芯片安装插入件（60）通过在半导体芯片（50）和插入件（20）之间执行引线键合而构成，其中连接到芯片（50）的端子（51）的端子（21）和分离的端子（22）形成在插入件（20）的上表面上。半导体芯片（30）安装在封装基板（10）的顶面上，插入件（60）粘接到芯片（30）的上部，并且在端子（22）和端子（11'）。当以这种方式配置具有组合成一个封装的多个半导体芯片的半导体器件时，可以容易地保证每个半导体芯片的KGD（Known-Good-Die），并且可以以高产量的良好单元制造半导体器件。此外，半导体芯片可以原样使用，而不限制其端子的位置，间距，信号布置等。

4. 发明申请

US20070230251A1 Nonvolatile Semiconductor Memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20070230251A1
公开(公告)日：2007-10-04
申请号：US11550335
申请日：2006-10-17
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
IPC分类号： G11C16/10
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译：通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

5. 发明授权

US6153493A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US6153493A
公开(公告)日：2000-11-28
申请号：US116880
申请日：1998-07-16
申请人： Hiromi Makimoto , Moriyoshi Nakashima , Kojiro Yuzuriha , Makoto Ooi , Jun Sumino
发明人： Hiromi Makimoto , Moriyoshi Nakashima , Kojiro Yuzuriha , Makoto Ooi , Jun Sumino
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76202
摘要： A field oxide film which is fine and having smaller upheaval of a bird's head is formed, so as to improve electrical characteristic of a conductive layer formed with end portions positioned on the field oxide film. A planarizing silicon film is formed on a silicon nitride film and a thermal oxide film, so as to planarize a concave generated between the thermal oxide film and a silicon nitride film. The planarizing silicon film is thermally oxidized, so as to form a planarizing thermal oxide film integrated with the thermal oxide film. Thereafter, the planarizing thermal oxide film is etched back to form the field oxide film, and the silicon nitride film and a polycrystalline silicon film are removed. Thereafter, the conductive layer with end portions positioned on the field oxide film is formed.
摘要翻译：形成精细且具有较小的鸟头动作的场氧化膜，从而改善形成在位于场氧化膜上的端部的导电层的电特性。在氮化硅膜和热氧化膜上形成平坦化硅膜，以平坦化在热氧化膜和氮化硅膜之间产生的凹。平坦化硅膜被热氧化，以形成与热氧化膜一体化的平坦化热氧化膜。此后，平面化热氧化膜被回蚀以形成场氧化物膜，并且去除氮化硅膜和多晶硅膜。此后，形成具有位于场氧化膜上的端部的导电层。

6. 发明授权

US5229645A Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5229645A
公开(公告)日：1993-07-20
申请号：US709607
申请日：1991-06-05
申请人： Moriyoshi Nakashima
发明人： Moriyoshi Nakashima
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L23/485 , H01L23/522
CPC分类号： H01L24/02 , H01L21/76819 , H01L23/5226 , H01L2224/0401 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/0105 , H01L2924/01082 , H01L2924/1306 , H01L2924/19043
摘要： The semiconductor device includes a silicon substrate, a conductor thin film formed over the surface of the silicon substrate with a first insulating film interposed therebetween, a second insulating film covering the upper surface of the conductor thin film, and an interconnection layer formed on the second insulating film. A contact hole is formed in the second insulating film and the conductor thin film and the interconnection layer are electrically connected to each other through the contact hole. An insulator layer or a conductor layer in an electrically floating state is selectively formed between the conductor thin film and the surface of the silicon substrate at least immediately below the contact hole. The semiconductor device is formed, for example, by selectively forming a conductor layer on the first insulating film, covering the exposed surface thereof with an insulating film, and then depositing the conductor thin film. In accordance with the semiconductor device and the manufacturing method thereof, even if the conductor thin film is penetrated by an anisotropic etching at the time of forming the contact hole, insulation between the silicon substrate and the conductor thin film is ensured without fail, and a highly reliable semiconductor device can be provided with high productivity, having no defect due to dielectric breakdown.
摘要翻译：半导体器件包括硅衬底，在硅衬底的表面上形成有介于其间的第一绝缘膜的导体薄膜，覆盖导体薄膜的上表面的第二绝缘膜和形成在第二绝缘膜上的互连层绝缘膜。在第二绝缘膜中形成接触孔，并且导体薄膜和互连层通过接触孔彼此电连接。至少在接触孔的正下方，选择性地在导体薄膜和硅衬底的表面之间形成电浮动状态的绝缘体层或导体层。半导体器件例如通过在第一绝缘膜上选择性地形成导体层，用绝缘膜覆盖其暴露表面，然后沉积导体薄膜而形成。根据半导体器件及其制造方法，即使在形成接触孔时导电薄膜被各向异性蚀刻穿透，也能够确保硅基板与导体薄膜之间的绝缘，可以提供高可靠性的半导体器件，具有高生产率，由于电介质击穿而没有缺陷。

7. 发明申请

US20080265433A1 INTERPOSER, SEMICONDUCTOR CHIP MOUNTED SUB-BOARD, AND SEMICONDUCTOR PACKAGE 有权
公开(公告)号：US20080265433A1
公开(公告)日：2008-10-30
申请号：US12164503
申请日：2008-06-30
申请人： Moriyoshi NAKASHIMA , Kazuo Kobayashi , Natsuo Ajika
发明人： Moriyoshi NAKASHIMA , Kazuo Kobayashi , Natsuo Ajika
IPC分类号： H01L23/49
CPC分类号： H01L25/0657 , H01L2224/48145 , H01L2224/48227 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2225/06575 , H01L2225/06596 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00012
摘要： A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on.Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.

8. 发明授权

US07420206B2 Interposer, semiconductor chip mounted sub-board, and semiconductor package 失效
标题翻译：内插器，半导体芯片安装子板和半导体封装
公开(公告)号：US07420206B2
公开(公告)日：2008-09-02
申请号：US11456913
申请日：2006-07-12
申请人： Moriyoshi Nakashima , Kazuo Kobayashi , Natsuo Ajika
发明人： Moriyoshi Nakashima , Kazuo Kobayashi , Natsuo Ajika
IPC分类号： H01L29/10
CPC分类号： H01L25/0657 , H01L2224/48145 , H01L2224/48227 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2225/06575 , H01L2225/06596 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00012
摘要： A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.
摘要翻译：可以制造具有高无缺陷率的半导体器件，使得可以在配置其上安装有多个半导体芯片的一个封装的半导体器件时容易地保证半导体芯片的KGD（已知好裸芯片）。使得每个半导体芯片可以在终端位置，间距，信号布置等方面没有限制。提供给半导体芯片安装的密封子板的突起附接到封装基板。多个半导体裸芯片设置在形成在半导体芯片安装密封子板和封装基板之间的空间中，使得布线成为可能。

9. 发明申请

US20080121878A1 INTERPOSER, SEMICONDUCTOR CHIP MOUNTED SUB-BOARD, AND SEMICONDUCTOR PACKAGE 失效
标题翻译：插件，半导体芯片安装子板和半导体封装
公开(公告)号：US20080121878A1
公开(公告)日：2008-05-29
申请号：US11456913
申请日：2006-07-12
申请人： Moriyoshi Nakashima , Kazuo Kobayashi , Natsuo Ajika
发明人： Moriyoshi Nakashima , Kazuo Kobayashi , Natsuo Ajika
IPC分类号： H01L23/58 , H01L29/40
CPC分类号： H01L25/0657 , H01L2224/48145 , H01L2224/48227 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2225/06575 , H01L2225/06596 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00012
摘要： A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on.Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.
摘要翻译：可以制造具有高无缺陷率的半导体器件，使得可以在配置其上安装有多个半导体芯片的一个封装的半导体器件时容易地保证半导体芯片的KGD（已知好裸芯片）。使得每个半导体芯片可以在终端位置，间距，信号布置等方面没有限制。提供给半导体芯片安装的密封子板的突起附接到封装基板。多个半导体裸芯片设置在形成在半导体芯片安装密封子板和封装基板之间的空间中，使得布线成为可能。

10. 发明授权

US08687455B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08687455B2
公开(公告)日：2014-04-01
申请号：US13205900
申请日：2011-08-09
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Moriyoshi Nakashima
IPC分类号： G11C8/00
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译：通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

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