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    • 5. 发明授权
    • Wireless communication control system and method thereof
    • 无线通信控制系统及其方法
    • US08036163B2
    • 2011-10-11
    • US12555463
    • 2009-09-08
    • Hideaki Kobayashi
    • Hideaki Kobayashi
    • H04W4/00
    • H04L41/5012H04L41/12H04L41/507H04W8/24H04W76/10H04W76/20H04W76/36
    • A wireless communications control system includes: a data server; a base station; and a plurality of wireless terminals, each exchanging data communications with the data server by establishing wireless communications with the base station. Each wireless terminal includes a control section for generating property information representing own property and a wireless communications section for transmitting that property information to the base station. The property information includes at least one of information indicating operating status of the wireless terminal, information identifying the wireless terminal itself, and information identifying the user of the wireless terminal. The data server includes a communications section for receiving the property information from the respective wireless terminals by way of the base station and a control section for choosing, by reference to the property information received, one of the wireless terminals to exchange the data communications with. The control section of the data server exchanges the data communications with the wireless terminal chosen.
    • 无线通信控制系统包括:数据服务器; 一个基站; 以及多个无线终端,每个无线终端通过与基站建立无线通信来与数据服务器进行数据通信。 每个无线终端包括用于产生表示自身属性的属性信息的控制部分和用于将该属性信息发送到基站的无线通信部分。 属性信息包括指示无线终端的操作状态的信息,识别无线终端本身的信息和识别无线终端的用户的信息中的至少一个。 数据服务器包括用于通过基站从各个无线终端接收属性信息的通信部分和用于通过参考所接收到的属性信息来选择一个无线终端来交换数据通信的控制部分。 数据服务器的控制部分与所选择的无线终端进行数据通信。
    • 7. 发明授权
    • Serial-to-parallel converter circuit and parallel-to-serial converter circuit
    • 串并转换电路和并 - 串转换电路
    • US07446680B2
    • 2008-11-04
    • US11844492
    • 2007-08-24
    • Hideaki Kobayashi
    • Hideaki Kobayashi
    • H03M9/00
    • H03M9/00
    • A parallel-to-serial converter selects variable-m1-bit parallel dummy data from m-bit parallel dummy data (0≦m1≦m) together with a n-bit parallel data signal synchronized with a first clock signal having a first frequency, and converts the selected (n+m1)-bit parallel data into a (n+m1)-bit serial data signal synchronized with a second clock signal having a frequency (n+m1) times the first frequency. A serial-to-parallel converter circuit selects n-bit serial data from the (n+m1) parallel data signal and converts the n-bit serial data into a n-bit parallel data signal synchronized with the first clock signal.
    • 并行/串行转换器从m位并行虚拟数据(0 <= m1 <= m)中选择可变m1位并行虚拟数据以及与具有第一个时钟信号的第一时钟信号同步的n位并行数据信号 并且将所选择的(n + m1)位并行数据转换为与具有第一频率的频率(n + m1)倍的第二时钟信号同步的(n + m1)位串行数据信号。 串并转换器电路从(n + m1)并行数据信号中选择n位串行数据,并将n位串行数据转换为与第一时钟信号同步的n位并行数据信号。
    • 8. 发明授权
    • Serial-to-parallel converter circuit and parallel-to-serial converter circuit
    • 串并转换电路和并 - 串转换电路
    • US07307559B2
    • 2007-12-11
    • US11359368
    • 2006-02-23
    • Hideaki Kobayashi
    • Hideaki Kobayashi
    • H03M9/00
    • H03M9/00
    • A parallel-to-serial converter selects variable-ml-bit parallel dummy data from m-bit parallel dummy data (0≦m1≦m) together with a n-bit parallel data signal synchronized with a first clock signal having a first frequency, and converts the selected (n+m1)-bit parallel data into a (n+m1)-bit serial data signal synchronized with a second clock signal having a frequency (n+m1) times the first frequency. A serial-to-parallel converter circuit selects n-bit serial data from the (n+m1) parallel data signal and converts the n-bit serial data into a n-bit parallel data signal synchronized with the first clock signal.
    • 并行到串行转换器从m位并行虚拟数据(0 <= m1 <= m)中选择可变毫比特并行虚拟数据以及与具有第一个时钟信号的第一时钟信号同步的n位并行数据信号 并且将所选择的(n + m1)位并行数据转换为与具有第一频率的频率(n + m1)倍的第二时钟信号同步的(n + m1)位串行数据信号。 串并转换器电路从(n + m1)并行数据信号中选择n位串行数据,并将n位串行数据转换为与第一时钟信号同步的n位并行数据信号。