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1. 发明申请

US20090106726A1 DESIGN STRUCTURES INCLUDING MEANS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES 有权
标题翻译：设计结构包括用于半导体器件中的横向电流承载能力改进的手段
公开(公告)号：US20090106726A1
公开(公告)日：2009-04-23
申请号：US11873711
申请日：2007-10-17
申请人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
发明人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： G06F17/50
CPC分类号： H01L21/76816 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.
摘要翻译：包括半导体结构的设计结构。半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。导电线路存在于N ILD层的至少两个ILD层中。导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

2. 发明申请

US20080122096A1 METHODS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES 失效
标题翻译：用于半导体器件中的横向电流承载能力改进的方法
公开(公告)号：US20080122096A1
公开(公告)日：2008-05-29
申请号：US11460314
申请日：2006-07-27
申请人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
发明人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76838 , H01L21/8249 , H01L23/53228 , H01L23/53257 , H01L23/53295 , H01L27/0623 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.
摘要翻译：半导体结构及其形成方法。半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。导电线路存在于N ILD层的至少两个ILD层中。导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

3. 发明授权

US07453151B2 Methods for lateral current carrying capability improvement in semiconductor devices 失效
标题翻译：半导体器件横向载流能力改善方法
公开(公告)号：US07453151B2
公开(公告)日：2008-11-18
申请号：US11460314
申请日：2006-07-27
申请人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
发明人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： H01L29/80
CPC分类号： H01L21/76838 , H01L21/8249 , H01L23/53228 , H01L23/53257 , H01L23/53295 , H01L27/0623 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.
摘要翻译：半导体结构及其形成方法。半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。导电线路存在于N ILD层的至少两个ILD层中。导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

4. 发明授权

US07904868B2 Structures including means for lateral current carrying capability improvement in semiconductor devices 有权
标题翻译：结构包括用于半导体器件中横向电流承载能力改进的装置
公开(公告)号：US07904868B2
公开(公告)日：2011-03-08
申请号：US11873711
申请日：2007-10-17
申请人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
发明人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： G06F17/50
CPC分类号： H01L21/76816 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.
摘要翻译：包括半导体结构的设计结构。半导体结构包括（a）衬底; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。导电线路存在于N ILD层的至少两个ILD层中。导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

5. 发明申请

US20080308940A1 LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：在半导体器件中的横向电流承载能力改进
公开(公告)号：US20080308940A1
公开(公告)日：2008-12-18
申请号：US12198196
申请日：2008-08-26
申请人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
发明人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： H01L23/522
CPC分类号： H01L21/76838 , H01L21/8249 , H01L23/53228 , H01L23/53257 , H01L23/53295 , H01L27/0623 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.
摘要翻译：半导体结构。半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。导电线路存在于N ILD层的至少两个ILD层中。导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

6. 发明申请

US20100210043A1 IN-LINE DEPTH MEASUREMENT OF THRU SILICON VIA 有权
标题翻译：通过硅片的在线深度测量
公开(公告)号：US20100210043A1
公开(公告)日：2010-08-19
申请号：US12371724
申请日：2009-02-16
申请人： Qizhi Liu , Ping-Chuan Wang , Kimball M. Watson , Zhijian J. Yang
发明人： Qizhi Liu , Ping-Chuan Wang , Kimball M. Watson , Zhijian J. Yang
IPC分类号： H01L21/66 , G06F19/00
CPC分类号： H01L22/34 , H01L2924/3011
摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.
摘要翻译：在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构，设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。在制造期间同时产生电阻测量沟槽结构和未填充TSV。

7. 发明授权

US07904273B2 In-line depth measurement for thru silicon via 有权
标题翻译：通过硅通孔的在线深度测量
公开(公告)号：US07904273B2
公开(公告)日：2011-03-08
申请号：US12371724
申请日：2009-02-16
申请人： Qizhi Liu , Ping-Chuan Wang , Kimball M. Watson , Zhijian J. Yang
发明人： Qizhi Liu , Ping-Chuan Wang , Kimball M. Watson , Zhijian J. Yang
IPC分类号： G06F19/00
CPC分类号： H01L22/34 , H01L2924/3011
摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.
摘要翻译：在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构，设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。在制造期间同时产生电阻测量沟槽结构和未填充TSV。

8. 发明申请

US20050199908A1 METHOD OF BASE FORMATION IN A BICMOS PROCESS 失效
标题翻译： BICMOS过程中基质形成的方法
公开(公告)号：US20050199908A1
公开(公告)日：2005-09-15
申请号：US10708598
申请日：2004-03-13
申请人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
发明人： Peter Geiss , Marwan Khater , Qizhi Liu , Randy Mann , Robert Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas Stricker
IPC分类号： H01L21/28 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/417 , H01L29/73 , H01L29/732 , H01L29/737 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

9. 发明申请

US20080268604A1 METHODS OF BASE FORMATION IN A BiCMOS PROCESS 失效
标题翻译： BiCMOS工艺中基质形成的方法
公开(公告)号：US20080268604A1
公开(公告)日：2008-10-30
申请号：US12128077
申请日：2008-05-28
申请人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
发明人： Peter J. Geiss , Marwan H. Khater , Qizhi Liu , Randy W. Mann , Robert J. Purtell , BethAnn Rainey , Jae-Sung Rieh , Andreas D. Stricker
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/28518 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/456 , H01L29/7371
摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.
摘要翻译：提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。凸起的外基极上面的硅化物以自对准的方式延伸到发射极。发射极通过间隔物与硅化物分离。

10. 发明申请

US20140021587A1 LOCAL WIRING FOR A BIPOLAR JUNCTION TRANSISTOR INCLUDING A SELF-ALIGNED EMITTER REGION 有权
标题翻译：用于包括自对准发射极区域的双极晶体管的本地布线
公开(公告)号：US20140021587A1
公开(公告)日：2014-01-23
申请号：US13551971
申请日：2012-07-18
申请人： David L. Harame , Zhong-Xiang He , Qizhi Liu
发明人： David L. Harame , Zhong-Xiang He , Qizhi Liu
IPC分类号： H01L29/66 , H01L29/73
CPC分类号： H01L29/66234 , H01L29/0804 , H01L29/66287 , H01L29/73 , H01L29/732
摘要： Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.
摘要翻译：本发明的方面提供了一种自对准发射极的双极晶体管。在一个实施例中，本发明提供了一种用于具有自对准牺牲发射器的双极晶体管的局部布线的方法，包括：执行蚀刻以去除牺牲发射极以在两个氮化物间隔物之间形成发射极开口; 将原位掺杂的发射体沉积到发射极开口中; 执行凹陷蚀刻以部分去除原位掺杂发射体的一部分; 在凹入的原位掺杂发射体上沉积二氧化硅层; 通过化学机械抛光使二氧化硅层平坦化; 在凹入的原位掺杂发射体上蚀刻发射极沟槽; 并通过化学机械抛光沉积钨并在发射器沟槽内形成钨布线。

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