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1. 发明申请

US20140021587A1 LOCAL WIRING FOR A BIPOLAR JUNCTION TRANSISTOR INCLUDING A SELF-ALIGNED EMITTER REGION 有权
标题翻译：用于包括自对准发射极区域的双极晶体管的本地布线
公开(公告)号：US20140021587A1
公开(公告)日：2014-01-23
申请号：US13551971
申请日：2012-07-18
申请人： David L. Harame , Zhong-Xiang He , Qizhi Liu
发明人： David L. Harame , Zhong-Xiang He , Qizhi Liu
IPC分类号： H01L29/66 , H01L29/73
CPC分类号： H01L29/66234 , H01L29/0804 , H01L29/66287 , H01L29/73 , H01L29/732
摘要： Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.
摘要翻译：本发明的方面提供了一种自对准发射极的双极晶体管。在一个实施例中，本发明提供了一种用于具有自对准牺牲发射器的双极晶体管的局部布线的方法，包括：执行蚀刻以去除牺牲发射极以在两个氮化物间隔物之间形成发射极开口; 将原位掺杂的发射体沉积到发射极开口中; 执行凹陷蚀刻以部分去除原位掺杂发射体的一部分; 在凹入的原位掺杂发射体上沉积二氧化硅层; 通过化学机械抛光使二氧化硅层平坦化; 在凹入的原位掺杂发射体上蚀刻发射极沟槽; 并通过化学机械抛光沉积钨并在发射器沟槽内形成钨布线。

2. 发明授权

US08841750B2 Local wiring for a bipolar junction transistor including a self-aligned emitter region 有权
标题翻译：包括自对准发射极区域的双极结型晶体管的局部布线
公开(公告)号：US08841750B2
公开(公告)日：2014-09-23
申请号：US13551971
申请日：2012-07-18
申请人： David L. Harame , Zhong-Xiang He , Qizhi Liu
发明人： David L. Harame , Zhong-Xiang He , Qizhi Liu
IPC分类号： H01L29/732 , H01L29/66 , H01L29/73 , H01L29/08
CPC分类号： H01L29/66234 , H01L29/0804 , H01L29/66287 , H01L29/73 , H01L29/732
摘要： Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.
摘要翻译：本发明的方面提供了一种自对准发射极的双极晶体管。在一个实施例中，本发明提供了一种用于具有自对准牺牲发射器的双极晶体管的局部布线的方法，包括：执行蚀刻以去除牺牲发射极以在两个氮化物间隔物之间形成发射极开口; 将原位掺杂的发射体沉积到发射极开口中; 执行凹陷蚀刻以部分去除原位掺杂发射体的一部分; 在凹入的原位掺杂发射体上沉积二氧化硅层; 通过化学机械抛光使二氧化硅层平坦化; 在凹入的原位掺杂发射体上蚀刻发射极沟槽; 并通过化学机械抛光沉积钨并在发射器沟槽内形成钨布线。

3. 发明授权

US09053939B2 Heterojunction bipolar transistor with epitaxial emitter stack to improve vertical scaling 有权
标题翻译：具有外延发射极堆叠的异质结双极晶体管，以改善垂直刻度
公开(公告)号：US09053939B2
公开(公告)日：2015-06-09
申请号：US13303248
申请日：2011-11-23
申请人： Thomas N. Adam , David L. Harame , Qizhi Liu , Alexander Reznicek
发明人： Thomas N. Adam , David L. Harame , Qizhi Liu , Alexander Reznicek
IPC分类号： H01L29/737 , H01L21/02 , H01L29/66 , H01L29/08 , H01L29/417 , H01L29/10
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/02439 , H01L21/02447 , H01L21/0245 , H01L21/02521 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L29/0817 , H01L29/1004 , H01L29/41708 , H01L29/66242 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p+Si1-xGex layer, formed above the n-type doped collector, that forms a p-type doped internal base of the HBT; a crystalline silicon cap formed on the p-type doped crystalline p+Si1-xGex layer, in which the crystalline silicon cap includes an n-type impurity and forms an n-type doped emitter of the HBT; and an n-type doped crystalline silicon emitter stack formed within an opening through an insulating layer to an upper surface of the crystalline silicon cap.
摘要翻译：异质结双极晶体管（HBT）可以包括在晶体硅衬底层的上部形成的n型掺杂晶体集电极; 形成在n型掺杂集电极上方的p型掺杂晶体p + Si1-xGex层，其形成HBT的p型掺杂内部基极; 形成在p型掺杂结晶p + Si1-xGex层上的晶体硅帽，其中晶体硅帽包括n型杂质并形成HBT的n型掺杂发射极; 以及形成在通过绝缘层的开口内的晶体硅帽的上表面的n型掺杂晶体硅发射极堆叠。

4. 发明授权

US08921194B2 PNP bipolar junction transistor fabrication using selective epitaxy 有权
标题翻译： PNP双极结晶体管制造使用选择性外延
公开(公告)号：US08921194B2
公开(公告)日：2014-12-30
申请号：US13294697
申请日：2011-11-11
申请人： David L. Harame , Qizhi Liu
发明人： David L. Harame , Qizhi Liu
IPC分类号： H01L21/331 , H01L21/8228 , H01L21/8224 , H01L29/66 , H01L27/082 , H01L29/737 , H01L29/10
CPC分类号： H01L29/735 , H01L21/8224 , H01L21/8228 , H01L27/0821 , H01L29/0649 , H01L29/0808 , H01L29/0826 , H01L29/1004 , H01L29/1008 , H01L29/16 , H01L29/6625 , H01L29/66272 , H01L29/7371
摘要： Lateral PNP bipolar junction transistors, methods for fabricating lateral PNP bipolar junction transistors, and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base.
摘要翻译：横向PNP双极结晶体管，用于制造横向PNP双极结型晶体管的方法，以及横向PNP双极结型晶体管的设计结构。横向PNP双极结晶体管的发射极和集电极由通过选择性外延生长工艺形成的p型半导体材料组成。源极和漏极各自直接接触用于形成发射极和集电极的器件区域的顶表面。基部触点可以形成在顶表面上并且覆盖限定在器件区域内的n型基极。发射极通过基座触点与收集器横向分开。另一个基底接触可以形成在由基部与另一个基部接触分离的器件区域中。

5. 发明申请

US20110312147A1 TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR 有权
标题翻译：具有侧向定义的内部基极到极端基底连接区域的晶体管结构和形成晶体管的方法
公开(公告)号：US20110312147A1
公开(公告)日：2011-12-22
申请号：US12967268
申请日：2010-12-14
申请人： David L. Harame , Russell T. Herrin , Qizhi Liu
发明人： David L. Harame , Russell T. Herrin , Qizhi Liu
IPC分类号： H01L21/331
CPC分类号： H01L29/0649 , H01L29/0821 , H01L29/1004 , H01L29/66242 , H01L29/66287 , H01L29/732 , H01L29/7375 , H01L29/7378
摘要： Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.
摘要翻译：公开了双极或异质结双极晶体管的实施例以及形成晶体管的方法。晶体管可以包含夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定的导电带限制到外部基极层连接区域以降低基极电阻 Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。该方法允许发射极与基极区域的自对准，并结合使用牺牲介电层，其必须足够厚以承受蚀刻和清洁过程，并且当导电带是随后形成。可以使用化学增强的高压，低温氧化（HIPOX）工艺来形成这种牺牲介电层。

6. 发明授权

US07002221B2 Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same 有权
公开(公告)号：US07002221B2
公开(公告)日：2006-02-21
申请号：US10604988
申请日：2003-08-29
申请人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
发明人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
IPC分类号： H01L23/62
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

7. 发明授权

US08927357B2 Junction field-effect transistor with raised source and drain regions formed by selective epitaxy 有权
标题翻译：通过选择性外延形成的具有升高的源极和漏极区的结场场效应晶体管
公开(公告)号：US08927357B2
公开(公告)日：2015-01-06
申请号：US13294731
申请日：2011-11-11
申请人： Kevin K. Chan , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
发明人： Kevin K. Chan , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L21/337 , H01L29/10 , H01L27/06 , H01L29/66 , H01L29/737 , H01L29/808 , H01L29/165 , H01L29/08
CPC分类号： H01L29/8086 , G06F17/5045 , H01L27/0623 , H01L29/0817 , H01L29/0826 , H01L29/1004 , H01L29/1058 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66242 , H01L29/66893 , H01L29/66901 , H01L29/732 , H01L29/7375 , H01L29/808
摘要： Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.
摘要翻译：结型场效应晶体管，用于制造结型场效应晶体管的方法，以及结型场效应晶体管的设计结构。结场效应晶体管的源极和漏极由通过选择性外延生长并与半导体层的顶表面直接接触的半导体材料组成。形成与在源极和漏极之间横向设置在半导体层中的沟道对准的栅极。源极，漏极和半导体层各自包括与包括栅极的第一半导体材料具有相反导电类型的第二半导体材料。

8. 发明申请

US20130214275A1 TRANSISTOR HAVING A NARROW IN-SUBSTRATE COLLECTOR REGION FOR REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR 有权
标题翻译：具有用于减少基极集电极结电容的窄层内基板收集器区域的晶体管和形成晶体管的方法
公开(公告)号：US20130214275A1
公开(公告)日：2013-08-22
申请号：US13401064
申请日：2012-02-21
申请人： James W. Adkisson , David L. Harame , Qizhi Liu
发明人： James W. Adkisson , David L. Harame , Qizhi Liu
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/732 , H01L29/1004 , H01L29/66234 , H01L29/66242 , H01L29/7371
摘要： Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region.
摘要翻译：公开了晶体管（例如，双极结型晶体管（BJT）或异质结双极晶体管（HBT））以及形成具有窄的衬底内集电极区域以减小基极 - 集电极结电容的晶体管的方法。晶体管在衬底内具有位于横向邻近沟槽隔离区域的集电极区域。相对薄的种子层覆盖沟槽隔离区域和收集器区域。该晶种层具有单晶中心，该晶体中心在集电极区域上方（例如由于固相外延再生长工艺）而上方且更宽，并且多晶外部部分。本征基底层外延沉积在种子层上，使得其类似地具有在集电极区域上方并且更宽的单晶中心部分。非本征基层是本征基层，并且具有从集电极垂直偏移的单晶非本征基本至本征基极连接区域。

9. 发明授权

US08492237B2 Methods of fabricating a bipolar junction transistor with a self-aligned emitter and base 有权
标题翻译：制造具有自对准发射极和基极的双极结型晶体管的方法
公开(公告)号：US08492237B2
公开(公告)日：2013-07-23
申请号：US13042902
申请日：2011-03-08
申请人： Kevin K. Chan , Erik M. Dahlstrom , Peter B. Gray , David L. Harame , Qizhi Liu
发明人： Kevin K. Chan , Erik M. Dahlstrom , Peter B. Gray , David L. Harame , Qizhi Liu
IPC分类号： H01L21/8222
CPC分类号： H01L29/73 , H01L21/28518 , H01L29/0821 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.
摘要翻译：用于制造具有自对准发射极和非本征基极的双极结型晶体管的方法，通过该方法制造的双极结型晶体管以及用于BiCMOS集成电路的设计结构。使用牺牲发射器基座制造双极结型晶体管，该牺牲发射器基座提供牺牲的心轴，以促进发射极和外部基极之间的自对准。随后去除牺牲发射器基座以打开延伸到本征基底的发射器窗口。在发射器窗口中形成发射极，其位于本征基极上。

10. 发明申请

US20130126944A1 HETEROJUNCTION BIPOLAR TRANSISTOR WITH EPITAXIAL EMITTER STACK TO IMPROVE VERTICAL SCALING 有权
标题翻译：具有外延发射体堆叠的异相双极晶体管以改善垂直刻度
公开(公告)号：US20130126944A1
公开(公告)日：2013-05-23
申请号：US13303248
申请日：2011-11-23
申请人： Thomas N. Adam , David L. Harame , Qizhi Liu , Alexander Reznicek
发明人： Thomas N. Adam , David L. Harame , Qizhi Liu , Alexander Reznicek
IPC分类号： H01L29/70 , H01L21/331
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/02439 , H01L21/02447 , H01L21/0245 , H01L21/02521 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L29/0817 , H01L29/1004 , H01L29/41708 , H01L29/66242 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p+Si1-xGex layer, formed above the n-type doped collector, that forms a p-type doped internal base of the HBT; a crystalline silicon cap formed on the p-type doped crystalline p+Si1-xGex layer, in which the crystalline silicon cap includes an n-type impurity and forms an n-type doped emitter of the HBT; and an n-type doped crystalline silicon emitter stack formed within an opening through an insulating layer to an upper surface of the crystalline silicon cap.
摘要翻译：异质结双极晶体管（HBT）可以包括在晶体硅衬底层的上部形成的n型掺杂晶体集电极; 形成在n型掺杂集电极上方的p型掺杂晶体p + Si1-xGex层，其形成HBT的p型掺杂内部基极; 形成在p型掺杂结晶p + Si1-xGex层上的晶体硅帽，其中晶体硅帽包括n型杂质并形成HBT的n型掺杂发射极; 以及形成在通过绝缘层的开口内的晶体硅帽的上表面的n型掺杂晶体硅发射极堆叠。

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