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1. 发明授权

US08698296B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08698296B2
公开(公告)日：2014-04-15
申请号：US12785488
申请日：2010-05-24
申请人： Naoto Taoka , Atsushi Nakamura , Naozumi Morino , Toshikazu Ishikawa , Nobuhiro Kinoshita
发明人： Naoto Taoka , Atsushi Nakamura , Naozumi Morino , Toshikazu Ishikawa , Nobuhiro Kinoshita
IPC分类号： H01L23/522 , H01L23/52 , H01L23/538
CPC分类号： H01L24/81 , H01L21/563 , H01L23/3128 , H01L23/5226 , H01L23/5283 , H01L23/5286 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05553 , H01L2224/05599 , H01L2224/06515 , H01L2224/1134 , H01L2224/13144 , H01L2224/14515 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48599 , H01L2224/49171 , H01L2224/49175 , H01L2224/4943 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/81193 , H01L2224/81203 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2224/85 , H01L2224/83 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/92247
摘要： The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).
摘要翻译：要提高半导体器件的可靠性。具有形成在其主表面上的多个焊盘的微计算机芯片（半导体芯片）以与芯片主表面相对的状态安装在布线基板的上表面上。耦合到形成在衬底上表面上的多个端子（接合引线）的焊盘包括多个第一焊盘，其中与流过其它焊盘的电流不同的独特电流流过多个第二焊盘，其中电流焊盘共同流动或不流动。第一焊盘或第二焊盘中的一个的另一个第一焊盘布置在第一焊盘的旁边。第一焊盘分别经由多个凸起（第一导电构件）电耦合到多个接合引线，而第二焊盘通过多个凸块（第二导电构件）接合到端子。

2. 发明申请

US20100301466A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100301466A1
公开(公告)日：2010-12-02
申请号：US12785488
申请日：2010-05-24
申请人： Naoto TAOKA , Atsushi Nakamura , Naozumi Morino , Toshikazu Ishikawa , Nobuhiro Kinoshita
发明人： Naoto TAOKA , Atsushi Nakamura , Naozumi Morino , Toshikazu Ishikawa , Nobuhiro Kinoshita
IPC分类号： H01L23/522 , H01L23/52 , H01L23/538
CPC分类号： H01L24/81 , H01L21/563 , H01L23/3128 , H01L23/5226 , H01L23/5283 , H01L23/5286 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05553 , H01L2224/05599 , H01L2224/06515 , H01L2224/1134 , H01L2224/13144 , H01L2224/14515 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48599 , H01L2224/49171 , H01L2224/49175 , H01L2224/4943 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/81193 , H01L2224/81203 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2224/85 , H01L2224/83 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/92247
摘要： The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).
摘要翻译：要提高半导体器件的可靠性。具有形成在其主表面上的多个焊盘的微计算机芯片（半导体芯片）以与芯片主表面相对的状态安装在布线基板的上表面上。耦合到形成在衬底上表面上的多个端子（接合引线）的焊盘包括多个第一焊盘，其中与流过其它焊盘的电流不同的独特电流流过多个第二焊盘，其中电流焊盘共同流动或不流动。第一焊盘或第二焊盘中的一个的另一个第一焊盘布置在第一焊盘的旁边。第一焊盘分别经由多个凸起（第一导电构件）电耦合到多个接合引线，而第二焊盘通过多个凸块（第二导电构件）接合到端子。

3. 发明申请

US20060180943A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060180943A1
公开(公告)日：2006-08-17
申请号：US11401284
申请日：2006-04-11
申请人： Takashi Miwa , Yasumi Tsutsumi , Masahiro Ichitani , Takanori Hashizume , Masamichi Sato , Naozumi Morino , Atsushi Nakamura , Saneaki Tamaki , Ikuo Kudo
发明人： Takashi Miwa , Yasumi Tsutsumi , Masahiro Ichitani , Takanori Hashizume , Masamichi Sato , Naozumi Morino , Atsushi Nakamura , Saneaki Tamaki , Ikuo Kudo
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L25/0657 , H01L23/5386 , H01L25/18 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： The present invention provides a semiconductor device having a stacked structure which realizes the miniaturization of a contour size and the reduction of thickness. The present invention also provides a semiconductor device which realizes high performance and high reliability in addition to the miniaturization of the contour size. The semiconductor device uses a package substrate on which bonding leads which are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads are formed. The semiconductor device further includes an address output circuit and a data input/output circuit which are also served for memory access and a signal processing circuit having a data processing function. A semiconductor chip in which bonding pads which are connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads which are connected to the bonding leads corresponding to the data terminals of the package substrate are distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.
摘要翻译：本发明提供一种具有层叠结构的半导体器件，其实现了轮廓尺寸的小型化和厚度的减小。本发明还提供了除了轮廓尺寸的小型化之外还实现高性能和高可靠性的半导体器件。半导体装置使用封装基板，在该封装基板上分别对应于分配给存储芯片的相对的第一和第二侧的地址和数据的接合焊盘形成的接合引线以及连接到接合引线的地址端子和数据端子形成。半导体器件还包括还用于存储器访问的地址输出电路和数据输入/输出电路以及具有数据处理功能的信号处理电路。一种半导体芯片，其中连接到与封装基板的地址端子相对应的接合引线的接合焊盘和连接到与封装基板的数据端子对应的接合引线的接合焊盘分配到四个侧面和上述存储芯片以堆叠结构安装在封装基板上。

4. 发明授权

US07061785B2 Stacked large-scale integrated circuit (LSI) semiconductor device with miniaturization and thinning of package 失效
标题翻译：堆叠大型集成电路（LSI）半导体器件，封装小型化和薄型化
公开(公告)号：US07061785B2
公开(公告)日：2006-06-13
申请号：US10606891
申请日：2003-06-27
申请人： Takashi Miwa , Yasumi Tsutsumi , Masahiro Ichitani , Takanori Hashizume , Masamichi Sato , Naozumi Morino , Atsushi Nakamura , Saneaki Tamaki , Ikuo Kudo
发明人： Takashi Miwa , Yasumi Tsutsumi , Masahiro Ichitani , Takanori Hashizume , Masamichi Sato , Naozumi Morino , Atsushi Nakamura , Saneaki Tamaki , Ikuo Kudo
IPC分类号： G11C5/06
CPC分类号： H01L25/0657 , H01L23/5386 , H01L25/18 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.
摘要翻译：半导体器件使用分别对应于分配到存储器芯片的相对的第一和第二侧的地址和数据的接合焊盘以及连接到接合引线的地址端子和数据端子分别形成有接合引线的封装基板。半导体器件还包括地址输出电路和用于存储器访问的数据输入/输出电路和具有数据处理功能的信号处理电路。一种半导体芯片，其具有连接到与封装基板的地址端子对应的接合引线的接合焊盘以及连接到与封装基板的数据端子相对应的接合引线的接合焊盘，并且分布在四边的两侧，上述存储芯片以堆叠结构安装在封装基板上。

5. 发明授权

US07286386B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07286386B2
公开(公告)日：2007-10-23
申请号：US11401284
申请日：2006-04-11
申请人： Takashi Miwa , Yasumi Tsutsumi , Masahiro Ichitani , Takanori Hashizume , Masamichi Sato , Naozumi Morino , Atsushi Nakamura , Saneaki Tamaki , Ikuo Kudo
发明人： Takashi Miwa , Yasumi Tsutsumi , Masahiro Ichitani , Takanori Hashizume , Masamichi Sato , Naozumi Morino , Atsushi Nakamura , Saneaki Tamaki , Ikuo Kudo
IPC分类号： G11C5/06 , H01L23/48
CPC分类号： H01L25/0657 , H01L23/5386 , H01L25/18 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure. Bonding leads arranged along at least one side of the substrate may include bonding leads of rectangular configuration having longer sides disposed at acute angles with respect to the side of the substrate.
摘要翻译：半导体器件使用分别对应于分配到存储器芯片的相对的第一和第二侧的地址和数据的接合焊盘以及连接到接合引线的地址端子和数据端子分别形成有接合引线的封装基板。半导体器件还包括地址输出电路和用于存储器访问的数据输入/输出电路和具有数据处理功能的信号处理电路。一种半导体芯片，其具有连接到与封装基板的地址端子对应的接合引线的接合焊盘以及连接到与封装基板的数据端子相对应的接合引线的接合焊盘，并且分布在四边的两侧，上述存储芯片以堆叠结构安装在封装基板上。沿着衬底的至少一侧布置的接合引线可以包括具有相对于衬底的侧面以锐角设置的长边的矩形构造的接合引线。

6. 发明授权

US08110878B2 Semiconductor device having a plurality of shallow wells 有权
标题翻译：具有多个浅井的半导体装置
公开(公告)号：US08110878B2
公开(公告)日：2012-02-07
申请号：US13179163
申请日：2011-07-08
申请人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
发明人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/01 , H01L27/12 , H01L31/0392 , H01L23/62
CPC分类号： H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L2224/05554
摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
摘要翻译：提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

7. 发明授权

US07982271B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07982271B2
公开(公告)日：2011-07-19
申请号：US12901858
申请日：2010-10-11
申请人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
发明人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/01 , H01L27/12 , H01L31/0392 , H01L23/62
CPC分类号： H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L2224/05554
摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
摘要翻译：提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

8. 发明授权

US07714357B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07714357B2
公开(公告)日：2010-05-11
申请号：US12253850
申请日：2008-10-17
申请人： Takahiro Hayashi , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
发明人： Takahiro Hayashi , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
IPC分类号： H01L29/74 , H01L23/52
CPC分类号： H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
摘要翻译：本发明的目的是提供一种能够减小半导体器件的平面尺寸的技术。在半导体衬底上形成输入/输出电路，接地布线和电源布线通过输入/输出电路，并且在其上形成用于焊盘的导电层。输入/输出电路由nMISFET形成区域和pMISFET形成区域中的MISFET元件形成，电阻元件形成区域中的电阻元件和用作保护元件的二极管元件形成区域中的二极管元件。连接到保护元件并位于接地布线和电源布线下方的布线在nMISFET形成区域和pMISFET形成区域之间以及接地布线和要连接的电源布线之间的拉出区域中拉出到导电层。

9. 发明授权

US08482038B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08482038B2
公开(公告)日：2013-07-09
申请号：US13545553
申请日：2012-07-10
申请人： Takayuki Sasaki , Yasuto Igarashi , Naozumi Morino
发明人： Takayuki Sasaki , Yasuto Igarashi , Naozumi Morino
IPC分类号： H01L27/118
CPC分类号： H04B3/32
摘要： A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.
摘要翻译：减少半导体装置中的串扰噪声等外部噪声的影响的技术，以防止电路发生故障。易受噪声影响的真实信号线和条形信号线，以及电平移位器电路的输入信号线的一部分以及用于屏蔽这些信号线的屏蔽线布置在I / O单元上。这样的I / O单元被并排放置以完成真正的信号线连接和条形信号线连接。这些导线布置成通过多个I / O单元并且彼此平行或多层。

10. 发明申请

US20110231694A1 DATA PROCESSING DEVICE AND MOBILE DEVICE 有权
标题翻译：数据处理设备和移动设备
公开(公告)号：US20110231694A1
公开(公告)日：2011-09-22
申请号：US13152676
申请日：2011-06-03
申请人： KAZUO SAKAMOTO , Naozumi Morino , Ikuo Kudo
发明人： KAZUO SAKAMOTO , Naozumi Morino , Ikuo Kudo
IPC分类号： G06F1/04
CPC分类号： G06F5/06 , G06F1/10
摘要： A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
摘要翻译：即使当诸如MMC卡的卡连接到其上时，也提供具有能够正确地锁存数据的存储卡接口的微型计算机。在具有与诸如存储卡的外部设备的接口的微型计算机中，接口单元设置有连接到外部端子的输出驱动器，用于输出时钟信号以输出时钟信号，并且具有能够传递时钟信号的等效负载电路，与从时钟信号路径中的输出驱动器之前的级中的任意位置提取的时钟信号相当于连接到外部端子的外部负载引起的延迟的延迟，以便产生用于锁存从外部端子输入的数据的时钟信号存储卡。

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