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1. 发明申请

US20070187823A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070187823A1
公开(公告)日：2007-08-16
申请号：US11783983
申请日：2007-04-13
申请人： Naotaka Tanaka , Tomio Iwasaki , Hideo Miura , Yasuyuki Nakajima , Tomoo Matsuzawa
发明人： Naotaka Tanaka , Tomio Iwasaki , Hideo Miura , Yasuyuki Nakajima , Tomoo Matsuzawa
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/563 , H01L23/3128 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/78 , H01L24/85 , H01L25/0657 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/1134 , H01L2224/13144 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/4807 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48453 , H01L2224/48465 , H01L2224/4851 , H01L2224/48624 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/78301 , H01L2224/85045 , H01L2224/85205 , H01L2225/06558 , H01L2225/06568 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01105 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19043 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20303 , H01L2924/20304 , H01L2924/20305 , H01L2924/20751 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2924/00011 , H01L2924/00015
摘要： An object of the present invention is to establish, for an LSI having a stacked interconnection structure of Cu interconnect/Low-k material, a narrow pitch wire bonding technique enabling a reduction in damage to a bonding pad and application similar to the conventional LSI of an aluminum interconnection. In a semiconductor device having a multilayer interconnection made of a Cu interconnect/Low-k dielectric material, the above-described object can be attained by a bonding pad structure in which all the wiring layers up to the uppermost cap interconnect are formed of a Cu wiring layer and a bonding pad portion formed of a Cu layer is equipped with a refractory intermediate metal layer such as Ti (titanium) filmor (tungsten) film on the Cu layer and an aluminum alloy layer on the intermediate metal layer.
摘要翻译：本发明的目的在于，对于具有Cu互连/ Low-k材料的堆叠互连结构的LSI，可以实现能够减少对焊盘的损伤的窄间距引线接合技术和类似于传统LSI的铝互连。在具有由Cu互连/ Low-k电介质材料制成的多层互连的半导体器件中，上述目的可以通过一种焊盘结构来实现，其中所有的布线层直到最上盖互连件都是由Cu 布线层和由Cu层形成的接合焊盘部分在Cu层上装有诸如Ti（钛）膜（钨）的耐火材料中间金属层和中间金属层上的铝合金层。

2. 发明申请

US20050001314A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050001314A1
公开(公告)日：2005-01-06
申请号：US10873251
申请日：2004-06-23
申请人： Naotaka Tanaka , Tomio Iwasaki , Hideo Miura , Yasuyuki Nakajima , Tomoo Matsuzawa
发明人： Naotaka Tanaka , Tomio Iwasaki , Hideo Miura , Yasuyuki Nakajima , Tomoo Matsuzawa
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/44 , H01L21/56 , H01L21/60 , H01L21/768 , H01L23/31 , H01L23/48 , H01L23/485 , H01L23/532 , H01L25/065
CPC分类号： H01L23/53238 , H01L21/563 , H01L23/3128 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/78 , H01L24/85 , H01L25/0657 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/1134 , H01L2224/13144 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/4807 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48453 , H01L2224/48465 , H01L2224/4851 , H01L2224/48624 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/78301 , H01L2224/85045 , H01L2224/85205 , H01L2225/06558 , H01L2225/06568 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01105 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19043 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20303 , H01L2924/20304 , H01L2924/20305 , H01L2924/20751 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2924/00011 , H01L2924/00015
摘要： An object of the present invention is to establish, for an LSI having a stacked interconnection structure of Cu interconnect/Low-k material, a narrow pitch wire bonding technique enabling a reduction in damage to a bonding pad and application similar to the conventional LSI of an aluminum interconnection. In a semiconductor device having a multilayer interconnection made of a Cu interconnect/Low-k dielectric material, the above-described object can be attained by a bonding pad structure in which all the wiring layers up to the uppermost cap interconnect are formed of a Cu wiring layer and a bonding pad portion formed of a Cu layer is equipped with a refractory intermediate metal layer such as Ti (titanium) filmor (tungsten) film on the Cu layer and an aluminum alloy layer on the intermediate metal layer.
摘要翻译：本发明的目的在于，对于具有Cu互连/ Low-k材料的堆叠互连结构的LSI，可以实现能够减少对焊盘的损伤的窄间距引线接合技术和类似于常规LSI的铝互连。在具有由Cu互连/ Low-k电介质材料制成的多层互连的半导体器件中，上述目的可以通过一种焊盘结构来实现，其中所有的布线层直到最上盖互连件都是由Cu 布线层和由Cu层形成的接合焊盘部分在Cu层上装有诸如Ti（钛）膜（钨）的耐火材料中间金属层和中间金属层上的铝合金层。

3. 发明授权

US07241685B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07241685B2
公开(公告)日：2007-07-10
申请号：US10390413
申请日：2003-03-18
申请人： Hiroshi Moriya , Tomio Iwasaki , Hideo Miura , Shinji Nishihara , Masashi Sahara
发明人： Hiroshi Moriya , Tomio Iwasaki , Hideo Miura , Shinji Nishihara , Masashi Sahara
IPC分类号： H01L21/44
CPC分类号： H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.
摘要翻译：提供一种具有降低短路可能性的布线结构的半导体器件及其制造方法。此外，提供了具有高可靠性的半导体器件。此外，提供了一种具有高产率的半导体器件。在半导体衬底的一个主表面侧形成布线，并且具有相邻导体层和主布线层的叠层结构。主配线层包含一个添加的元素以防止迁移。相邻的导体层由用于防止主要构成元素和主配线层的添加元素扩散到相邻导体层下方的基板中的材料形成，并且添加元素在靠近界面处的位置的浓度与相邻的导体层间隔开的主配线层的添加元素的浓度相比，相邻的导体层和主布线层的电位低。

4. 发明授权

US07217971B2 Miniaturized semiconductor device with improved dielectric properties 有权
标题翻译：具有改善介电特性的小型半导体器件
公开(公告)号：US07217971B2
公开(公告)日：2007-05-15
申请号：US10848473
申请日：2004-05-17
申请人： Tomio Iwasaki , Hiroshi Moriya , Hideo Miura , Shuji Ikeda
发明人： Tomio Iwasaki , Hiroshi Moriya , Hideo Miura , Shuji Ikeda
IPC分类号： H01L31/119
CPC分类号： H01L21/823462 , H01L21/28097 , H01L21/28185 , H01L21/28194 , H01L21/28518 , H01L21/31604 , H01L21/823412 , H01L27/1085 , H01L27/10873 , H01L29/045 , H01L29/4908 , H01L29/4975 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/78696
摘要： Diffusion layers 2–5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2–5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.
摘要翻译：在硅衬底1上形成扩散层2-5，并且在这些扩散层2-5上形成栅电介质膜6,7和栅电极8,9，以便成为MOS晶体管。氧化锆或氧化铪被用作栅介质膜6,7的主要成分。栅介质膜6,7例如通过CVD形成。作为基板1，使用表面为（111）晶面的其中之一，以防止氧扩散到硅基板1或栅电极8,9中。在使用表面为（111）晶面的基板的情况下，在使用表面为（001）晶面的硅基板的情况下，氧的扩散系数小于1/100，氧气扩散被控制。因此，控制氧扩散，防止漏电流的产生，提高性能。实现了具有高可靠性并且能够防止伴随小型化的特性劣化的半导体器件。

5. 发明授权

US06639263B2 Semiconductor device with copper wiring connected to storage capacitor 失效
标题翻译：具有铜线的半导体器件连接到存储电容器
公开(公告)号：US06639263B2
公开(公告)日：2003-10-28
申请号：US10255714
申请日：2002-09-27
申请人： Yukihiro Kumagai , Hideo Miura , Hiroyuki Ohta , Tomio Iwasaki , Isamu Asano
发明人： Yukihiro Kumagai , Hideo Miura , Hiroyuki Ohta , Tomio Iwasaki , Isamu Asano
IPC分类号： H01L27108
CPC分类号： H01L21/7687 , H01L23/53238 , H01L27/10814 , H01L27/10882 , H01L27/10894 , H01L27/11502 , H01L27/11507 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： It is an object of the present invention to provide a high-reliability semiconductor device having a storage capacitor and wiring using copper for a main conductive film. Under the above object, the present invention provides a semiconductor device comprising: a semiconductor substrate; a storage capacitor formed on the main surface side of the semiconductor substrate and being a first electrode and a second electrode arranged so as to put a capacitor insulation film; a wiring conductor formed on the main surface side of the semiconductor substrate and including the copper (Cu) element; and a first film formed on the surface of the wiring conductor; wherein a material configuring the first film and a material configuring the first electrode and/or the second electrode include the same element.
摘要翻译：本发明的目的是提供一种具有存储电容器和使用铜作为主导电膜的布线的高可靠性半导体器件。根据上述目的，本发明提供一种半导体器件，包括：半导体衬底; 形成在所述半导体基板的所述主面侧的作为第一电极的保持电容器和布置成放置电容器绝缘膜的第二电极; 形成在所述半导体衬底的主表面侧并且包括所述铜（Cu）元件的布线导体; 以及形成在所述布线导体的表面上的第一膜; 其中构成第一膜的材料和构成第一电极和/或第二电极的材料包括相同的元件。

6. 发明授权

US06617691B2 Semiconductor device 失效
公开(公告)号：US06617691B2
公开(公告)日：2003-09-09
申请号：US10252534
申请日：2002-09-24
申请人： Takashi Nakajima , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Shinji Nishihara , Masashi Sahara , Kentaro Yamada , Masayuki Suzuki
发明人： Takashi Nakajima , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Shinji Nishihara , Masashi Sahara , Kentaro Yamada , Masayuki Suzuki
IPC分类号： H01L2348
CPC分类号： H01L23/485 , H01L23/53257 , H01L2924/0002 , H01L2924/00
摘要： The object of the invention is to provide such a highly reliable semiconductor device as no defect such as the breakage of a tungsten conductor occurs. This object is achieved by the following means, i.e., a molybdenum film, a tungsten film and another molybdenum film are deposited in this order on an interlayer dielectric film formed on a silicon substrate.

7. 发明授权

US06548904B2 Semiconductor device having a capacitor and a metal interconnect layer with tungsten as a main constituent material and containing molybdenum 失效
标题翻译：具有电容器和具有钨作为主要构成材料并含有钼的金属互连层的半导体器件
公开(公告)号：US06548904B2
公开(公告)日：2003-04-15
申请号：US10252685
申请日：2002-09-24
申请人： Tomio Iwasaki , Hideo Miura , Takashi Nakajima , Hiroyuki Ohta , Shinji Nishihara , Masashi Sahara
发明人： Tomio Iwasaki , Hideo Miura , Takashi Nakajima , Hiroyuki Ohta , Shinji Nishihara , Masashi Sahara
IPC分类号： H01L2348
CPC分类号： H01L23/53257 , H01L27/10814 , H01L27/10894 , H01L28/55 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device, which comprises a capacitor component comprising a first electrode, an oxide film with a high dielectric constant or ferroelectricity in contact with the first electrode and a second electrode in contact with the oxide film, as formed in this order, on one principal side of a silicon substrate with a metal wiring layer formed thereon, such problems as breaking of tungsten interconnect, lowering of reliability, lowering of yield, etc. of semi-conductor devices can be solved by using molybdenum-containing tungsten as the material of metal interconnect layer.
摘要翻译：在包括第一电极的电容器组件，具有高介电常数或与第一电极接触的铁电性的氧化膜和与该氧化物膜接触的第二电极的电容器组件中，在其上形成有金属布线层的硅衬底的主面上，通过使用含钼钨作为材料，可以解决半导体器件的钨互连断裂，可靠性降低，成品率降低等问题金属互连层。

8. 发明授权

US06472754B2 Semiconductor device with improved arrangements to avoid breakage of tungsten interconnector 失效
标题翻译：具有改进布置以避免钨互连器断裂的半导体器件
公开(公告)号：US06472754B2
公开(公告)日：2002-10-29
申请号：US09822489
申请日：2001-04-02
申请人： Takashi Nakajima , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Shinji Nishihara , Masashi Sahara , Kentaro Yamada , Masayuki Suzuki
发明人： Takashi Nakajima , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Shinji Nishihara , Masashi Sahara , Kentaro Yamada , Masayuki Suzuki
IPC分类号： H01L2348
CPC分类号： H01L23/485 , H01L23/53257 , H01L2924/0002 , H01L2924/00
摘要： The object of the invention is to provide such a highly reliable semiconductor device as no defect such as the breakage of a tungsten conductor occurs. This object is achieved by the following means, i.e., a molybdenum film, a tungsten film and another molybdenum film are deposited in this order on an interlayer dielectric film formed on a silicon substrate.
摘要翻译：本发明的目的是提供这样一种高度可靠的半导体器件，不会出现诸如钨导体断裂的缺陷。该目的通过以下方式实现，即，将钼膜，钨膜和另一种钼膜依次沉积在形成在硅衬底上的层间电介质膜上。

9. 发明授权

US07701062B2 Semiconductor device and method for producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07701062B2
公开(公告)日：2010-04-20
申请号：US11834081
申请日：2007-08-06
申请人： Tomio Iwasaki , Hideo Miura
发明人： Tomio Iwasaki , Hideo Miura
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L23/53228 , H01L23/53242 , H01L23/53252 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|ap−an|/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|bp−bn|/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}
摘要翻译：提供的是具有分层互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜被接触与导体膜。在该器件中，用于导体膜和相邻膜的材料被选择成使得构成具有导体膜的最小自由能和短边的平面的矩形单位电池的短边面ap之间的差，，构成具有相邻膜的最小自由能的平面的矩形单元电池，矩形单位电池的长边，bp之间的差异为{| ap-an | / ap}×100 = A（％）构成具有相邻膜的最小自由能的构成平面的矩形单位电池的导体膜和长边bn的最小自由能的平面{| bp-bn | / bp}×100 = B （％）满足{A + B×（ap / bp）} <13的不等式。在此，导体膜的扩散被延迟。

10. 发明申请

US20060183324A1 Semiconductor device and method for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060183324A1
公开(公告)日：2006-08-17
申请号：US11392540
申请日：2006-03-30
申请人： Tomio Iwasaki , Hideo Miura
发明人： Tomio Iwasaki , Hideo Miura
IPC分类号： H01L21/44
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L23/53228 , H01L23/53242 , H01L23/53252 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|ap−an|/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|bp−bn|/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}
摘要翻译：提供了一种具有层状互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜与导体膜。在该器件中，用于导体膜和相邻膜的材料被选择成使构成具有最小自由能的平面的矩形单元电池的短边，即< 导体薄膜和构成具有相邻薄膜的最小自由能的平面的矩形单元电池的短边，即_{n x100 = A（％）和构成该矩阵单位单元的长边，b P 之间的差异构成具有相邻膜的最小自由能的平面的矩形单位电池的导体膜和长边的最小自由能的平面{| b＆lt; p＆lt; x100 = B（％）满足{A + Bx（a _{p b＆lt; p＆lt; p＆gt;）} <13。在此，导体膜的扩散被延迟。}}

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