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1. 发明申请

US20050095765A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050095765A1
公开(公告)日：2005-05-05
申请号：US10800749
申请日：2004-03-16
申请人： Takashi Saiki , Hiroyuki Ohta , Hiroyuki Kanata
发明人： Takashi Saiki , Hiroyuki Ohta , Hiroyuki Kanata
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L21/337
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.
摘要翻译：通过栅极电极掩蔽下的离子注入形成延伸区域，然后在栅极电极和第一侧壁间隔物的掩蔽下注入在源极和漏极中包含的杂质上具有扩散抑制功能的物质，以便在其表面层内形成半导体衬底并与第一侧壁间隔物对齐，从而形成非晶扩散抑制区域。

2. 发明授权

US07663187B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07663187B2
公开(公告)日：2010-02-16
申请号：US11984738
申请日：2007-11-21
申请人： Takashi Saiki , Hiroyuki Ohta , Hiroyuki Kanata
发明人： Takashi Saiki , Hiroyuki Ohta , Hiroyuki Kanata
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.
摘要翻译：通过栅极电极掩蔽下的离子注入形成延伸区域，然后在栅极电极和第一侧壁间隔物的掩蔽下注入在源极和漏极中包含的杂质上具有扩散抑制功能的物质，以便在其表面层内形成半导体衬底并与第一侧壁间隔物对齐，从而形成非晶扩散抑制区域。

3. 发明申请

US20080203475A1 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US20080203475A1
公开(公告)日：2008-08-28
申请号：US11984738
申请日：2007-11-21
申请人： Takashi Saiki , Hiroyuki Ohta , Hiroyuki Kanata
发明人： Takashi Saiki , Hiroyuki Ohta , Hiroyuki Kanata
IPC分类号： H01L29/78
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.

4. 发明授权

US07321151B2 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US07321151B2
公开(公告)日：2008-01-22
申请号：US10800749
申请日：2004-03-16
申请人： Takashi Saiki , Hiroyuki Ohta , Hiroyuki Kanata
发明人： Takashi Saiki , Hiroyuki Ohta , Hiroyuki Kanata
IPC分类号： H01L29/76
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.

5. 发明申请

US20080206948A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080206948A1
公开(公告)日：2008-08-28
申请号：US11984737
申请日：2007-11-21
申请人： Takashi Saiki , Hiroyuki Ohta , Hiroyuki Kanata
发明人： Takashi Saiki , Hiroyuki Ohta , Hiroyuki Kanata
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.
摘要翻译：通过栅极电极掩蔽下的离子注入形成延伸区域，然后在栅极电极和第一侧壁间隔物的掩蔽下注入在源极和漏极中包含的杂质上具有扩散抑制功能的物质，以便在其表面层内形成半导体衬底并与第一侧壁间隔物对齐，从而形成非晶扩散抑制区域。

6. 发明授权

US5667923A Charged particle beam exposure compensating proximity effect 失效
标题翻译：带电粒子束曝光补偿邻近效应
公开(公告)号：US5667923A
公开(公告)日：1997-09-16
申请号：US638864
申请日：1996-04-29
申请人： Hiroyuki Kanata
发明人： Hiroyuki Kanata
IPC分类号： H01L21/027 , G03F7/20 , H01J37/302
CPC分类号： B82Y10/00 , B82Y40/00 , G03F7/2061 , H01J37/3026 , H01J37/3174 , H01J2237/31764 , H01J2237/31769 , Y10S430/143
摘要： A subject pattern and a lower layer pattern are divided into small regions of a constant dimension using identical mesh of division. Considering of the spreading of charged particle beam due to backward scattering, the small region is set to be, for example, a few .mu.m square. An irradiation energy on each small region is determined by taking backward scattering from lower level pattern into account. Calculation is simplified because a pattern is represented by a pattern areal density. A region with a lower level pattern and a region without a lower level pattern can be exposured by charged particle beam with a comparable accuracy.
摘要翻译：主题图案和下层图案使用相同的划分网格划分为恒定尺寸的小区域。考虑到由于反向散射引起的带电粒子束的扩展，小区域被设定为例如几个平方米。通过从较低级别的模式考虑反向散射来确定每个小区域上的照射能量。计算简化，因为图案由图案面密度表示。具有较低水平图案的区域和不具有较低水平图案的区域可以以相当的精度被带电粒子束曝光。

7. 发明授权

US5783367A Process for production of semiconductor device and resist developing apparatus used therein 失效
标题翻译：用于制造半导体器件和抗蚀剂显影装置的方法
公开(公告)号：US5783367A
公开(公告)日：1998-07-21
申请号：US379025
申请日：1995-01-27
申请人： Takashi Maruyama , Tatsuo Chijimatsu , Koichi Kobayashi , Keiko Yano , Hiroyuki Kanata
发明人： Takashi Maruyama , Tatsuo Chijimatsu , Koichi Kobayashi , Keiko Yano , Hiroyuki Kanata
IPC分类号： G03F7/30
CPC分类号： G03F7/30 , G03F7/3021 , Y10S134/902
摘要： In the production of semiconductor devices, a pattern-wise exposed resist coating is developed with a developer to form a resist pattern corresponding to the pattern of exposure radiation on an article to be fabricated. The development being carried out with a developer consisting of one or more organic solvents, in at least two stages and in each stage of the development, the development is interrupted when a substantial permeation of the developer of a surface portion of the pattern-forming area of the resist pattern in which the resist pattern remains is completed, and the developed resist coating is dried between this stage and the following development stages. The development of the exposed resist coating is carried out by using a developing apparatus which comprises at least one set of developer-supplying system and rinsing solution-supplying system, and a conveyor means for guiding the article carrying the resist coating.
摘要翻译：在制造半导体器件时，用显影剂显影图案曝光的抗蚀剂涂层，以形成对应于要制造的制品上的曝光辐射图案的抗蚀剂图案。在一个由一种或多种有机溶剂组成的显影剂的显影中，至少在两个阶段和在显影的每一个阶段中进行显影，当图形形成区域的表面部分的显影剂的显着渗透其中抗蚀剂图案保留的抗蚀剂图案完成，并且显影的抗蚀剂涂层在该阶段和随后的显影阶段之间被干燥。曝光的抗蚀剂涂层的开发通过使用包括至少一组显影剂供应系统和冲洗溶液供应系统的显影装置和用于引导携带抗蚀剂涂层的物品的输送装置来进行。

8. 发明授权

US07585739B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07585739B2
公开(公告)日：2009-09-08
申请号：US11984737
申请日：2007-11-21
申请人： Takashi Saiki , Hiroyuki Ohta , Hiroyuki Kanata
发明人： Takashi Saiki , Hiroyuki Ohta , Hiroyuki Kanata
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.
摘要翻译：通过栅极电极掩蔽下的离子注入形成延伸区域，然后在栅极电极和第一侧壁间隔物的掩蔽下注入在源极和漏极中包含的杂质上具有扩散抑制功能的物质，以便在其表面层内形成半导体衬底并与第一侧壁间隔物对齐，从而形成非晶扩散抑制区域。

9. 发明授权

US6033134A Resist developing apparatus used in process for production of semiconductor device 失效
标题翻译：用于制造半导体器件的抗蚀剂显影装置
公开(公告)号：US6033134A
公开(公告)日：2000-03-07
申请号：US38105
申请日：1998-03-11
申请人： Takashi Maruyama , Tatsuo Chijimatsu , Koichi Kobayashi , Keiko Yano , Hiroyuki Kanata
发明人： Takashi Maruyama , Tatsuo Chijimatsu , Koichi Kobayashi , Keiko Yano , Hiroyuki Kanata
IPC分类号： G03F7/30 , G03D5/00
CPC分类号： G03F7/30 , G03F7/3021 , Y10S134/902
摘要： In the production of semiconductor devices, a pattern-wise exposed resist coating is developed with a developer to form a resist pattern corresponding to the pattern of exposure radiation on an article to be fabricated. The development being carried out with a developer consisting of one or more organic solvents, in at least two stages and in each stage of the development, the development is interrupted when a substantial permeation of the developer of a surface portion of the pattern-forming area of the resist pattern in which the resist pattern remains is completed, and the developed resist coating is dried between this stage and the following development stages. The development of the exposed resist coating is carried out by using a developing apparatus which comprises at least one set of developer-supplying system and rinsing solution-supplying system, and a conveyor means for guiding the article carrying the resist coating.
摘要翻译：在制造半导体器件时，用显影剂显影图案曝光的抗蚀剂涂层，以形成对应于要制造的制品上的曝光辐射图案的抗蚀剂图案。在一个由一种或多种有机溶剂组成的显影剂的显影中，至少在两个阶段和在显影的每个阶段中进行显影，当图案形成区域的表面部分的显影剂的显着渗透其中抗蚀剂图案保留的抗蚀剂图案完成，并且显影的抗蚀剂涂层在该阶段和随后的显影阶段之间被干燥。曝光的抗蚀剂涂层的开发通过使用包括至少一组显影剂供应系统和冲洗溶液供应系统的显影装置和用于引导携带抗蚀剂涂层的物品的输送装置来进行。

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