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1. 发明授权

US06232653B1 TSOP type semiconductor device 失效
标题翻译： TSOP型半导体器件
公开(公告)号：US06232653B1
公开(公告)日：2001-05-15
申请号：US09270500
申请日：1999-03-17
申请人： Naotaka Tanaka , Akihiro Yaguchi , Ryuji Kohno , Kiyomi Kojima , Takeshi Terasaki , Hideo Miura , Junichi Arita , Chikako Imura
发明人： Naotaka Tanaka , Akihiro Yaguchi , Ryuji Kohno , Kiyomi Kojima , Takeshi Terasaki , Hideo Miura , Junichi Arita , Chikako Imura
IPC分类号： H01L2348
CPC分类号： H01L23/4951 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/32014 , H01L2224/32245 , H01L2224/451 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/49175 , H01L2224/73215 , H01L2224/92147 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2224/05599
摘要： A TSOP type semiconductor device having a LOC structure employing a copper (alloy) type frame prevents resin cracks that occur in a reliability test such as a temperature cycle test. The TSOP type semiconductor device has narrower common inner leads where a resin crack would be likely to occur first, and has a thinner chip.
摘要翻译：具有采用铜（合金）型框架的LOC结构的TSOP型半导体器件防止了在诸如温度循环测试的可靠性测试中发生的树脂裂纹。 TSOP型半导体器件具有较窄的公共内引线，其中首先可能发生树脂裂纹，并且具有更薄的芯片。

2. 发明授权

US06876073B2 Semiconductor device and contractor for inspection 失效
标题翻译：半导体器件和承包商进行检查
公开(公告)号：US06876073B2
公开(公告)日：2005-04-05
申请号：US10260348
申请日：2002-10-01
申请人： Hideo Miura , Ryuji Kohno
发明人： Hideo Miura , Ryuji Kohno
IPC分类号： H01R33/76 , G01R1/073 , H01L21/66 , H01L23/00 , H01L23/485 , H01R13/533 , H05K3/32 , H01L23/02 , H01L23/34
CPC分类号： H01L24/05 , G01R1/073 , H01L2224/05624 , H01L2224/85424 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , H01L2924/351 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor device superior in heat dissipation in which the exchanging of chips can be readily performed is realized by mounting, through means distinct from bonding or connecting, a LSI chip on an interconnection substrate having substantially no difference in thermal conductivity between the LSI chip and the substrate. The semiconductor device is provided on an interconnection substrate 6 with electrode terminals 7 of cantilever structure, an interconnection layer 8 for electrical connection among the electrode terminals 7, an interconnection layer 12 for electrical connection to outer portions, and fitting portions 9 formed in a cover 5, the substrate 6 and the cover 5 being connected by the fitting portions. The chips 1 and 2 are electrically contacted through the terminals 7 without using any bonding or connecting, so that the mounting and detachment of the cover 5 and the substrate can be readily performed.
摘要翻译：通过在LSI芯片和LSI芯片之间基本上没有导热性差异的互连基板上安装LSI芯片，通过不同于粘接或连接的方式，实现了易于进行芯片交换的散热优良的半导体器件。基质。半导体器件设置在具有悬臂结构的电极端子7的互连基板6上，用于在电极端子7之间电连接的互连层8，用于与外部电连接的互连层12以及形成在盖子中的嵌合部分9 如图5所示，基板6和盖5通过嵌合部连接。芯片1和2通过端子7电接触而不使用任何结合或连接，从而可以容易地执行盖5和基板的安装和拆卸。

3. 发明申请

US20050032252A1 Testing apparatus for carrying out inspection of a semiconductor device 有权
标题翻译：用于对半导体器件进行检查的测试装置
公开(公告)号：US20050032252A1
公开(公告)日：2005-02-10
申请号：US10934046
申请日：2004-09-03
申请人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Hideyuki Aoki
发明人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Hideyuki Aoki
IPC分类号： G01R1/06 , G01R1/073 , G01R31/28 , H01L21/66 , G01R31/02 , G01R31/26
CPC分类号： G01R1/07314
摘要： A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device formed on the wafer. The testing process includes a step bringing a testing apparatus into contact with test electrodes of the semiconductor device. The testing apparatus has a contactor including a plurality of probes that come into contact with the test electrodes of the semiconductor device to be tested, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; a substrate on which electrodes electrically communicated to the contactor by a conducting device. The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes.
摘要翻译：制造半导体器件的方法具有在晶片的主表面上形成半导体器件的形成工艺和用于测试形成在晶片上的半导体器件的缺陷的测试过程。测试过程包括使测试设备与半导体器件的测试电极接触的步骤。测试装置具有接触器，该接触器包括与待测半导体器件的测试电极接触的多个探针，以及与探针电连接并设置在与探针相对的表面上的二次电极; 电极通过导电装置与接触器电连通的基板。导电装置形成为在探针与测试电极接触的状态下施加到导电装置的应力大于在探针不与测试电极接触的状态下施加到导电装置的应力。

4. 发明授权

US06977514B2 Probe structure 失效
标题翻译：探头结构
公开(公告)号：US06977514B2
公开(公告)日：2005-12-20
申请号：US10625566
申请日：2003-07-24
申请人： Ryuji Kohno , Tatsuya Nagata , Hiroya Shimizu , Toshio Miyatake , Hideo Miura
发明人： Ryuji Kohno , Tatsuya Nagata , Hiroya Shimizu , Toshio Miyatake , Hideo Miura
IPC分类号： G01R1/073 , H01L21/66 , G01R31/28
CPC分类号： G01R1/07378
摘要： A probe structure is provided in which secondary electrodes of a main base material and probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, and an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.
摘要翻译：提供了一种探针结构，其中形成主基材和探针的二次电极可以在基板侧电连接到基板侧的电极，即使在大面积上形成大量的探针，使得晶片内的大量LSI 可以在晶片测试过程中一次性测试，并且可以提高测试过程的效率。在探针结构中，由具有高刚性材料的插入体配置在其中形成有探针的主基材和基板侧之间，并且其中形成有探针的主基材的二次电极电连接到电极在基板侧经由插入件。

5. 发明授权

US06714030B2 Semiconductor inspection apparatus 失效
标题翻译：半导体检测仪器
公开(公告)号：US06714030B2
公开(公告)日：2004-03-30
申请号：US10390412
申请日：2003-03-18
申请人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
发明人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
IPC分类号： G01R3102
CPC分类号： H01L22/32 , G01R1/06711 , G01R1/06738 , G01R1/07314 , G01R3/00 , H01L23/13 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes. A method of manufacturing the semiconductor inspection apparatus comprises the steps of forming a cover film on a surface of the silicon substrate and forming a plurality of probes of a polygonal cone shape or a circular cone shape through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a beam or a diaphragm for each probe through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a through hole corresponding to the probe through etching after patterning by photolithography, and after the cover film is removed, forming an insulating film on the surface of the silicon substrate, forming a metal film on a surface of the insulating film, and forming a wiring lead through etching after patterning by photolithography.
摘要翻译：可以一次共同地检查多个半导体器件的半导体检查装置，由于探针的精度等，以前难以进行。一种制造半导体检查装置的方法包括以下步骤：在硅衬底的表面上形成覆盖膜，并通过光刻图案化之后通过蚀刻形成多个锥形或圆锥形的多个探针，被去除，再次在硅衬底的表面上形成覆盖膜，并且通过光刻在图案化之后通过蚀刻形成用于每个探针的光束或隔膜，在除去覆盖膜之后，再次在硅表面上形成覆盖膜在通过光刻图案化之后通过蚀刻形成与探针对应的通孔，并且在除去覆盖膜之后，在硅衬底的表面上形成绝缘膜，在绝缘膜的表面上形成金属膜，以及通过光刻在图案化之后通过蚀刻形成布线引线。

6. 发明授权

US06548315B2 Manufacture method for semiconductor inspection apparatus 失效
公开(公告)号：US06548315B2
公开(公告)日：2003-04-15
申请号：US10057921
申请日：2002-01-29
申请人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
发明人： Ryuji Kohno , Hideo Miura , Yoshishige Endo , Masatoshi Kanamaru , Atsushi Hosogane , Hideyuki Aoki , Naoto Ban
IPC分类号： H01L2166
CPC分类号： H01L22/32 , G01R1/06711 , G01R1/06738 , G01R1/07314 , G01R3/00 , H01L23/13 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes. A method of manufacturing the semiconductor inspection apparatus comprises the steps of forming a cover film on a surface of the silicon substrate and forming a plurality of probes of a polygonal cone shape or a circular cone shape through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a beam or a diaphragm for each probe through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a through hole corresponding to the probe through etching after patterning by photolithography, and after the cover film is removed, forming an insulating film on the surface of the silicon substrate, forming a metal film on a surface of the insulating film, and forming a wiring lead through etching after patterning by photolithography.

7. 发明授权

US06864695B2 Semiconductor device testing apparatus and semiconductor device manufacturing method using it 失效
标题翻译：半导体器件测试装置及其使用的半导体器件制造方法
公开(公告)号：US06864695B2
公开(公告)日：2005-03-08
申请号：US09925375
申请日：2001-08-10
申请人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Naoto Ban
发明人： Ryuji Kohno , Hideo Miura , Masatoshi Kanamaru , Hiroya Shimizu , Naoto Ban
IPC分类号： G01R1/073 , G01R3/00 , G01R31/28 , H01L21/66 , G01R31/02
CPC分类号： G01R3/00 , G01R1/07357
摘要： Since each wiring line is formed on one surface of the associated beam at a prescribed width over the entire length of the beam, the beam has the same sectional shape taken in the width direction at any point along an arbitrary longitudinal direction of the beam. As a result, the second moment of area, which is determined by the shapes of the beam and the wiring line, is uniform. This prevents a problem of the curvature of a beam varying locally when the beam is bent by a prescribed amount due to contact of the probe with a pad of a subject body. This, in turn, prevents local concentration of stress in the beams and thereby prevents breakage of the beam. Therefore, the probe structure can be miniaturized while the strength of the beams is kept at a required level, whereby a semiconductor device testing apparatus capable of accommodating many probes can be realized.
摘要翻译：由于每个布线在波束的整个长度上以规定的宽度形成在相关联的光束的一个表面上，所以光束在沿着光束的任意纵向方向的任何点处具有在宽度方向上取下的截面形状。结果，由光束和布线的形状确定的面积的第二时刻是均匀的。这防止了当由于探针与被检体的垫接触而使光束弯曲预定量时局部变化的光束曲率的问题。这反过来又防止梁中的局部应力集中，从而防止梁的断裂。因此，能够将光束的强度保持在所要求的水平，能够使探头结构小型化，能够实现容纳多个探针的半导体装置的测试装置。

8. 发明授权

US06864568B2 Packaging device for holding a plurality of semiconductor devices to be inspected 失效
标题翻译：用于保持待检查的多个半导体器件的封装装置
公开(公告)号：US06864568B2
公开(公告)日：2005-03-08
申请号：US10252546
申请日：2002-09-24
申请人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
发明人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
IPC分类号： G01R31/26 , G01R1/04 , G01R1/073 , H01L21/66 , H01L23/02
CPC分类号： G01R1/0483 , H01L2924/0002 , H01L2924/00
摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.
摘要翻译：一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件并且延伸到包装装置的外部，使得探针连接到每个导电构件。

9. 发明授权

US06614246B1 Probe structure 失效
标题翻译：探头结构
公开(公告)号：US06614246B1
公开(公告)日：2003-09-02
申请号：US09648452
申请日：2000-08-28
申请人： Ryuji Kohno , Tatsuya Nagata , Hiroya Shimizu , Toshio Miyatake , Hideo Miura
发明人： Ryuji Kohno , Tatsuya Nagata , Hiroya Shimizu , Toshio Miyatake , Hideo Miura
IPC分类号： G01R1073
CPC分类号： G01R1/07378
摘要： The invention provides a probe structure in which secondary electrodes of a main base material in which probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, whereby an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.
摘要翻译：本发明提供了一种探针结构，其中形成探针的主要基底材料的二次电极即使在大面积形成大量探针的情况下也可以与衬底侧的电极电连接，从而使大量的LSIs 可以在晶片测试过程中一次性地测试晶片，从而可以提高测试过程的效率。在探针结构中，由具有高刚性材料的插入体配置在其中形成有探针的主基材和基板侧之间，并且其中形成有探针的主基材的二次电极电连接到电极在基板侧经由插入件。

10. 发明授权

US06465264B1 Method for producing semiconductor device and apparatus usable therein 失效
标题翻译：用于制造半导体器件的方法和可用于其中的装置
公开(公告)号：US06465264B1
公开(公告)日：2002-10-15
申请号：US09654612
申请日：2000-09-01
申请人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
发明人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
IPC分类号： G01R3126
CPC分类号： G01R1/0483 , H01L2924/0002 , H01L2924/00
摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.
摘要翻译：一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件并且延伸到包装装置的外部，使得探针连接到每个导电构件。

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