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1. 发明授权

US5153847A Arithmetic processor using signed digit representation of internal operands 失效
标题翻译：使用内部操作数的符号位表示的算术处理器
公开(公告)号：US5153847A
公开(公告)日：1992-10-06
申请号：US599275
申请日：1990-10-16
申请人： Naofumi Takagi , Tsuguyasu Hatsuda , Toru Kakiage , Takashi Taniguchi , Tamotsu Nishiyama
发明人： Naofumi Takagi , Tsuguyasu Hatsuda , Toru Kakiage , Takashi Taniguchi , Tamotsu Nishiyama
IPC分类号： G06F7/48 , G06F7/52 , G06F7/537 , G06F7/544
CPC分类号： G06F7/544 , G06F7/4824 , G06F7/523 , G06F7/5338 , G06F7/5375
摘要： This invention discloses an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers. The arithmetic processor further comprises first means for adding a portion of the two numbers where both digits are present, second means for causing a lower order portion where only one of the numbers has a digit present to directly become part of the sum, third means for retaining or outputting a carry created by the first means, and fourth means for adding the carry created in each add stage of the adder tree to the later add stages of the adder tree to obtain the sum.
摘要翻译：本发明公开了一种算术处理器，它将内部算术运算符表示为有符号位数，每个数字的数字可以具有正值，零值或负值，并且执行多个数字的加法，每个数字的最高有效位相对于到其他数字。算术处理器包括加法器树，该加法器树被相加以使得一对所述多个数字被相加以获得部分和，并且连续地添加另外的部分和对，以获得所有数字的最终和。算术处理器还包括第一装置，用于添加两个数字存在的两个数字的一部分;第二装置，用于引起较低阶部分，其中只有一个数字存在的数字直接成为总和的一部分;第三装置，保存或输出由第一装置产生的进位，以及第四装置，用于将加法器树的每个加法阶段中产生的进位加到加法器树的稍后的加法阶段以获得和。

2. 发明授权

US5206825A Arithmetic processor using signed-digit representation of external operands 失效
标题翻译：算术处理器使用外部操作数的有符号表示法
公开(公告)号：US5206825A
公开(公告)日：1993-04-27
申请号：US857644
申请日：1992-03-24
申请人： Naofumi Takagi , Tsuguyasu Hatsuda , Toru Kakiage , Takashi Taniguchi , Tamotsu Nishiyama
发明人： Naofumi Takagi , Tsuguyasu Hatsuda , Toru Kakiage , Takashi Taniguchi , Tamotsu Nishiyama
IPC分类号： G06F7/48 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F7/4824 , G06F7/5375
摘要： This an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers. The arithmetic processor further comprises first means for adding a portion of the two numbers where both digits are present, second means for causing a lower order portion where only one of the numbers has a digit present to directly become part of the sum, third means for retaining or outputting a carry created by the first means, and fourth means for adding the carry created in each add stage of the adder tree to the later add stages of the adder tree to obtain the sum.
摘要翻译：这是一个算术处理器，它将内部算术操作数表示为有符号位数，每个数字的数字可能具有正值，零值或负值，并且执行多个数字的加法，每个数字的最高有效位相对于其他数字。算术处理器包括加法器树，该加法器树被相加以使得一对所述多个数字被相加以获得部分和，并且连续地添加另外的部分和对，以获得所有数字的最终和。算术处理器还包括第一装置，用于添加两个数字存在的两个数字的一部分;第二装置，用于引起较低阶部分，其中只有一个数字存在的数字直接成为总和的一部分;第三装置，保存或输出由第一装置产生的进位，以及第四装置，用于将加法器树的每个加法阶段中产生的进位加到加法器树的稍后的加法阶段以获得和。

3. 发明授权

US4866657A Adder circuitry utilizing redundant signed digit operands 失效
标题翻译：使用冗余有符号数字操作数的加法器电路
公开(公告)号：US4866657A
公开(公告)日：1989-09-12
申请号：US86967
申请日：1987-08-18
申请人： Tamotsu Nishiyama , Shigeo Kuninobu , Naofumi Takagi , Takashi Taniguchi
发明人： Tamotsu Nishiyama , Shigeo Kuninobu , Naofumi Takagi , Takashi Taniguchi
IPC分类号： G06F7/48 , G06F7/537
CPC分类号： G06F7/4824 , G06F7/5375
摘要： A high speed arithmetic processor and adder circuitry thereof are disclosed in which carry (borrow) propagation is never more than one digit. Addition (or subtraction) are performed by: (a) determining an intermediate carry (or borrow) at the i-th order position and an intermediate sum (or difference) at the i-th order position from the addend (or subtrahend) and the augend (or minuend) and (b) determining the sum (or difference) of the intermediate sum (or difference) at the i-th order position and the intermediate carry (or borrow) at the (i-1)-th or next-lower-order position. Logic equations, truth tables and circuitry are disclosed for implementing several embodiments of the invention.
摘要翻译：公开了一种高速算术处理器及其加法器电路，其中进位（借位）传播永远不超过一位数。通过以下方式执行加法（或减法）：（a）确定第i级位置的中间进位（或借位）以及从加数（或减数）和第i级位置的中间和（或差）加强（或调节）和（b）确定第i-1级位置上的中间总和（或差异）与第（i-1）或下一级位置。公开了用于实现本发明的几个实施例的逻辑方程，真值表和电路。

4. 发明授权

US4866655A Arithmetic processor and divider using redundant signed digit 失效
标题翻译：算术处理器和分频器使用冗余有符号数字
公开(公告)号：US4866655A
公开(公告)日：1989-09-12
申请号：US74892
申请日：1987-07-17
申请人： Tamotsu Nishiyama , Shigeo Kuninobu , Naofumi Takagi , Takashi Taniguchi
发明人： Tamotsu Nishiyama , Shigeo Kuninobu , Naofumi Takagi , Takashi Taniguchi
IPC分类号： G06F7/48 , G06F7/537
CPC分类号： G06F7/4824 , G06F7/5375
摘要： An arithmetic processor is disclosed for performing arithmetic operations utilizing an arithmetic operand represented by a signed digit expression having a plurality of digits which may have a positive, zero or negative value. The processor comprises: first circuitry coupled to receive a signal related to the most significant digit of a signed digit expression number Y having nonnegative (or nonpositive) digits other than the most significant digit, and for providing in response to a control signal, a signal representing the logical negation or inversion of the sign of the most significant digit; second circuitry coupled to receive at least one signal related to digits other than the most significant digit of the number Y, and for providing in response to a control signal, at least one signal representing the logical negation or inversion of those digits; and third circuitry coupled to receive a signal related to the least significant digit of the number Y, and for providing in response to a control signal, a signal representing the least significant digit plus 1 (or minus 1). The first and second circuitry invert the signs of the digits of the number Y, and the third circuitry adds (or subtracts) 1 from the least significant digit. The processor also includes circuitry coupled to receive the signals provided by the first, second and third circuitry and a signal representing a number X, and providing a signal representing the sum or difference of the numbers X and Y depending on the control signal.
摘要翻译：公开了一种算术处理器，用于利用由具有多个可能具有正，零或负值的数字的有符号数字表达式表示的算术运算数进行算术运算。该处理器包括：第一电路，被耦合以接收与具有除最高有效位之外的非负（或非正））数字的有符号数字表达式数Y的最高有效位相关的信号，并且响应于控制信号提供信号代表最重要数字的符号的逻辑否定或倒置; 第二电路，被耦合以接收与数字Y以外的数字相关的至少一个信号，并且响应于控制信号提供表示这些数字的逻辑否定或反转的至少一个信号; 以及第三电路，被耦合以接收与数字Y的最低有效位相关的信号，并且响应于控制信号提供表示最低有效数字加上1（或1）的信号。第一和第二电路反转数字Y的数字的符号，并且第三电路从最低有效数字加1（或减1）。处理器还包括耦合以接收由第一，第二和第三电路提供的信号的电路，以及表示数字X的信号，并根据控制信号提供表示数字X和Y的和或差的信号。

5. 发明授权

US4864528A Arithmetic processor and multiplier using redundant signed digit arithmetic 失效
标题翻译：使用冗余符号位运算的算术处理器和乘法器
公开(公告)号：US4864528A
公开(公告)日：1989-09-05
申请号：US74971
申请日：1987-07-17
申请人： Tamotsu Nishiyama , Shigeo Kuninobu , Naofumi Takagi , Takashi Taniguchi
发明人： Tamotsu Nishiyama , Shigeo Kuninobu , Naofumi Takagi , Takashi Taniguchi
IPC分类号： G06F7/48 , G06F7/537
CPC分类号： G06F7/4824 , G06F7/5375
摘要： A high speed processor including a multiplier is disclosed. The multiplier includes a multiplier recorder circuit which may record multipliers in groups of digits, and intermediate partial product generators which generate partial products from the recorded digits and a multiplicand. Addition/subtraction is then carried out on the intermediate partial products generated by the partial product generators. The processor may operate using signed digit expressions.
摘要翻译：公开了一种包括乘法器的高速处理器。乘法器包括可记录数字组的乘法器的乘法器记录器电路和从记录的数字和被乘数产生部分乘积的中间部分乘积生成器。然后对由部分积发生器产生的中间部分积进行加法/减法。处理器可以使用带符号数字表达式操作。

6. 发明授权

US08319228B2 Resin composition for optical semiconductor device, optical-semiconductor-device lead frame obtained using the same, and optical semiconductor device 有权
标题翻译：用于光学半导体器件的树脂组合物，使用其的光学半导体器件引线框架和光学半导体器件
公开(公告)号：US08319228B2
公开(公告)日：2012-11-27
申请号：US12875515
申请日：2010-09-03
申请人： Takashi Taniguchi , Kazuhiro Fuke , Hiroshi Noro , Hisataka Ito
发明人： Takashi Taniguchi , Kazuhiro Fuke , Hiroshi Noro , Hisataka Ito
IPC分类号： H01L35/24 , H01L29/26
CPC分类号： C08L63/00 , C08G59/3245 , C08G59/4215 , H01L2224/48091 , H01L2224/48247 , C08L83/04 , H01L2924/00014
摘要： The present invention relates to a resin composition for optical semiconductor devices, the resin composition including the following ingredients (A) to (D): (A) an epoxy resin; (B) a curing agent; (C) a polyorganosiloxane; and (D) a white pigment.
摘要翻译：本发明涉及一种用于光学半导体器件的树脂组合物，该树脂组合物包括以下成分（A）至（D）：（A）环氧树脂; （B）固化剂; （C）聚有机硅氧烷; 和（D）白色颜料。

7. 发明申请

US20100297202A1 PLANAR ANTENNA AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：平面天线及其制造方法
公开(公告)号：US20100297202A1
公开(公告)日：2010-11-25
申请号：US12812565
申请日：2009-02-05
申请人： Hiroto Okumura , Masaaki Shimagaki , Takashi Taniguchi
发明人： Hiroto Okumura , Masaaki Shimagaki , Takashi Taniguchi
IPC分类号： A61K9/10 , C09K3/00 , A61K47/36 , A61K8/00 , A61K8/73 , A23L1/05 , A23L1/0522 , A61K8/04 , A61P27/02
CPC分类号： A61Q19/00 , A61K8/042 , A61K8/73 , A61K9/0014 , A61K9/06 , A61K9/10 , A61K47/36 , C08B37/0039 , C08J3/05 , C08J3/075 , C08J2305/00 , C08J2305/12 , C08L5/00 , C08L5/12
摘要： Disclosed is an aqueous dispersion containing polysaccharide particulate gels, which is characterized by containing particulate gels substantially composed of a polysaccharide. The aqueous dispersion containing polysaccharide particulate gels is also characterized in that shapes of the particulate gels are maintained even after the particulate gels are heated for 30 minutes at 95° C. in an aqueous medium. Namely, disclosed is an aqueous dispersion containing polysaccharide particulate gels, wherein the particulate gels are composed of a polysaccharide and have shapes that can be maintained even after 30-minute heating in an aqueous medium of 95° C.
摘要翻译：公开了含有多糖颗粒凝胶的水分散体，其特征在于含有基本上由多糖组成的颗粒状凝胶。含有多糖颗粒凝胶的含水分散体的特征还在于，即使在颗粒状凝胶在水性介质中在95℃下加热30分钟之后也保持颗粒状凝胶的形状。即，公开了含有多糖粒状凝胶的水分散体，其中，所述颗粒状凝胶由多糖构成，即使在95℃的水性介质中加热30分钟后也能够维持。

8. 发明授权

US07659949B2 Backlight unit and liquid crystal display employing the same 有权
标题翻译：背光单元和使用其的液晶显示器
公开(公告)号：US07659949B2
公开(公告)日：2010-02-09
申请号：US11718294
申请日：2005-10-25
申请人： Shuji Sawada , Takashi Taniguchi
发明人： Shuji Sawada , Takashi Taniguchi
IPC分类号： G02F1/1333
CPC分类号： G02B6/0081 , G02F1/133308 , G02F1/133615 , G02F2201/465
摘要： A backlight unit (2) comprising a shallow box type case (3) having low profile sidewalls and opening upward, a light guide plate (7) in the box type case (3), and a supporting frame (11) containing optical members such as a linear light source (8) and an optical sheet (10) and securing the optical members in place by being fitted in the opening. A first engaging portion (4) is provided on the inside of the sidewall of the box type case (3) and second engaging portions (121-124) are provided on the outer surface of the sidewall of the supporting frame (11) being fitted in the upper opening of the box type case (3). A locking means (14) is attached to the second engaging portion such that the locking means (14) engages with and locks the first engaging portion when the first and second engaging portions engage with each other, thus preventing unfastening of the supporting frame. A liquid crystal display employing the backlight unit is also provided.
摘要翻译：一种背光单元（2），包括具有低剖面侧壁并向上开口的浅盒型壳体（3），盒型壳体（3）中的导光板（7）和包含光学构件的支撑框架作为线性光源（8）和光学片（10），并且通过装配在开口中将光学构件固定就位。第一接合部分（4）设置在盒式壳体（3）的侧壁的内侧，并且第二接合部分（121-124）设置在支撑框架（11）的侧壁的外表面上，在盒式箱体（3）的上部开口处。锁定装置（14）附接到第二接合部分，使得当第一和第二接合部分彼此接合时，锁定装置（14）与第一接合部分接合并锁定，从而防止支撑框架的松开。还提供了采用背光单元的液晶显示器。

9. 发明申请

US20090078851A1 Far Ultraviolet With High Luminance Emitting High-Purity Hexagonal Boron Nitride Monocrystalline Powder And Method Of Manufacturing The Same 有权
标题翻译：具有高亮度发射高纯度六方氮化硼单晶粉末的远紫外线及其制造方法
公开(公告)号：US20090078851A1
公开(公告)日：2009-03-26
申请号：US11988033
申请日：2006-07-03
申请人： Kenji Watanabe , Takashi Taniguchi , Hisao Kanda
发明人： Kenji Watanabe , Takashi Taniguchi , Hisao Kanda
IPC分类号： G01J1/32 , C09K11/08 , H01J1/62
CPC分类号： C04B35/583 , B01J3/062 , B01J2203/0645 , B01J2203/066 , C01B21/064 , C01P2002/76 , C01P2002/84 , C01P2006/80 , C04B2235/3852 , C04B2235/767 , C09K11/63 , G01T3/06
摘要： While high-purity hexagonal boron nitride monocrystal (hBN) obtained by way of a high temperature/high-pressure treatment in the presence of a high-purity solvent has excellent properties in terms of far-UV luminescence characteristics, it has drawbacks including that it can be easily adversely affected by mechanical vibrations and impetus, that monocrystal shows a poor morphological retentiveness and that the luminescence characteristics fluctuate to shift the selected and set wavelength. The present invention can overcome the drawbacks of being easily affected by vibrations and showing a poor morphological retentiveness by grinding down the monocrystal obtained by a solvent/refining process into powder and applying the powder to a light emitting surface. Thus, the present invention provides crystal powder to be used for a far-UV luminescence device showing excellent luminescence characteristics that are stable and do not fluctuate.
摘要翻译：虽然在高纯度溶剂存在下通过高温/高压处理获得的高纯度六方氮化硼单晶（hBN）在远紫外发光特性方面具有优异的性能，但其缺点包括：可以容易地受到机械振动和动力的不利影响，单晶显示出差的形态保持性，并且发光特性波动以移动所选择的和设定的波长。本发明可以克服通过将通过溶剂/精制过程获得的单晶研磨成粉末并将粉末施加到发光表面上的容易受振动影响并且显示不良形态保持性的缺点。因此，本发明提供了用于远紫外发光装置的结晶粉末，其表现出稳定且不波动的优异的发光特性。

10. 发明申请

US20070266896A1 Siloxane-Based Coating Material, Optical Article, and Production Method of Siloxane-Based Coating Material 审中-公开
标题翻译：硅氧烷基涂料，光学制品和硅氧烷基涂料的制备方法
公开(公告)号：US20070266896A1
公开(公告)日：2007-11-22
申请号：US11628798
申请日：2005-06-10
申请人： Mitsuhito Suwa , Hiroshi Hosono , Sayaka Takeda , Takashi Taniguchi , Hisashi Minamiguchi
发明人： Mitsuhito Suwa , Hiroshi Hosono , Sayaka Takeda , Takashi Taniguchi , Hisashi Minamiguchi
IPC分类号： C09D183/04 , B32B7/02 , C09D5/16 , C08J7/04
CPC分类号： C09D5/006 , C08K3/36 , C09D7/61 , C09D7/67 , C09D7/68 , C09D183/04 , G02B1/105 , G02B1/11 , G02B1/14
摘要： The invention provides a coating material containing silica fine particles, a siloxane compound, and a curing agent and giving an even coating film in the case it is used for forming a coating film. The invention gives a siloxane-based coating material excellent in storage stability and giving high surface hardness of a coating film when the coating material is used for forming the coating film. The invention also provides an optical article excellent in anti-reflection property and scratching resistance.
摘要翻译：本发明提供了含有二氧化硅微粒，硅氧烷化合物和固化剂的涂料，并且在用于形成涂膜的情况下得到均匀的涂膜。本发明提供了当涂料用于形成涂膜时，保存稳定性优异且赋予涂膜高表面硬度的硅氧烷类涂料。本发明还提供了抗反射性和抗划伤性优异的光学制品。

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