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1. 发明授权

US6031258A High DC current stagger power/ground pad 失效
标题翻译：高直流电流交错电源/接地垫
公开(公告)号：US6031258A
公开(公告)日：2000-02-29
申请号：US36351
申请日：1998-03-06
申请人： Nalini Ranjan , Henry Yang , Yi-Hen Wei , Gregg Bardel
发明人： Nalini Ranjan , Henry Yang , Yi-Hen Wei , Gregg Bardel
IPC分类号： H01L23/485 , H01L23/528 , H01L27/10
CPC分类号： H01L24/06 , H01L23/5283 , H01L2224/05554 , H01L2224/06153 , H01L2224/4943 , H01L24/49 , H01L2924/00014 , H01L2924/00015 , H01L2924/01014 , H01L2924/01074 , H01L2924/14
摘要： Improved conductive pads and conductive lines for use on integrated circuit chips include one or more conductive layers having a wider width than convention conductive lines for improved current and power carrying capacity. A layer of insulating and shock resistant is included over said layers of wider width, and additional pads can be formed on said layer of insulating and shock resistant material. Additional improved conductive pads are formed on the integrated circuit chip over a region containing a conductive line. The improved pads and conductive lines provide high power and current carrying capacity, and simultaneously allow for high pad density on an integrated circuit chip. Said pads and conductive lines can include a layer of metal which is electrically insulated using upper and lower layers of insulating material, with this layer of metal providing shock resistance particularly to such lower layer of insulating material.
摘要翻译：用于集成电路芯片的改进的导电焊盘和导线包括一个或多个导电层，其具有比常规导电线宽的宽度，以改善电流和功率承载能力。在所述较宽宽度的层上包括绝缘和抗冲击层，并且可以在所述绝缘和抗冲击材料层上形成附加的焊盘。在包含导电线的区域上的集成电路芯片上形成附加的改进的导电焊盘。改进的焊盘和导线提供高功率和电流承载能力，同时允许集成电路芯片上的高焊盘密度。所述焊盘和导线可以包括使用上下绝缘材料层电绝缘的金属层，该金属层特别提供对这种较低绝缘材料层的抗冲击性。

2. 发明授权

US06265899B1 Single rail domino logic for four-phase clocking scheme 有权
标题翻译：单轨多米诺骨牌逻辑四相计时方案
公开(公告)号：US06265899B1
公开(公告)日：2001-07-24
申请号：US09326161
申请日：1999-06-04
申请人： Saleh Abdel-Hafeez , Nalini Ranjan
发明人： Saleh Abdel-Hafeez , Nalini Ranjan
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A single rail domino logic circuit using a four-phase clocking scheme. A stacked PMOS pair provides a quarter clock cycle precharge time. The quarter clock cycle precharge time allows for placement of an additional inverter in the output signal path to form both an output signal and a complement of the output signal for use in subsequent logic stages.
摘要翻译：使用四相时钟方案的单轨多米诺骨牌逻辑电路。堆叠的PMOS对提供四分之一时钟周期的预充电时间。四分之一时钟周期预充电时间允许在输出信号路径中放置附加的反相器以形成用于后续逻辑级的输出信号和输出信号的互补。

3. 发明授权

US6005432A Voltage level shift system and method 失效
标题翻译：电压电平转换系统及方法
公开(公告)号：US6005432A
公开(公告)日：1999-12-21
申请号：US53555
申请日：1998-04-01
申请人： Xiaoyi Guo , Nalini Ranjan
发明人： Xiaoyi Guo , Nalini Ranjan
IPC分类号： H03K19/0185 , G06F5/00
CPC分类号： H03K19/018521
摘要： A voltage level shift system transitions a voltage signal between two components and includes a first inverter, a signal pass subsystem, a pull-up transistor, a second inverter, and a third inverter. The first inverter is coupled to the signal pass subsystem. The signal pass subsystem is coupled to the pull-up transistor, the second inverter, and the third inverter. The signal pass subsystem includes a first passgate and a second passgate. When an input voltage transitions from a logic low to a logic high, the first inverter inverts the logic high input signal to a logic low and passes this signal through the passgate subsystem. The second inverter receives the logic low signal and immediately inverts it to transition the output signal from a low logic to a logic high. The logic high output signal, turns off the pull-up transistor. When the input signal transitions from a logic high to a logic low, the first inverter receives the signal and generates a logic low signal that passes through the passgate subsystem. The second inverter receives the logic low signal and immediately inverts it to transition the output signal from a logic high to a logic low. The logic low signal places the pull-up transistor in an on state to turn off the p-device in the circuit. A method for transitioning a voltage signal between two components is also disclosed.
摘要翻译：电压电平移位系统转换两个部件之间的电压信号，并且包括第一反相器，信号传递子系统，上拉晶体管，第二反相器和第三反相器。第一个反相器耦合到信号传递子系统。信号传递子系统耦合到上拉晶体管，第二反相器和第三反相器。信号传递子系统包括第一传递门和第二传递门。当输入电压从逻辑低电平转换为逻辑高电平时，第一个反相器将逻辑高输入信号反相为逻辑低电平，并将该信号传递通过门电路子系统。第二个反相器接收逻辑低电平信号，并立即将其反相，将输出信号从低逻辑转换为逻辑高电平。逻辑高输出信号，关闭上拉晶体管。当输入信号从逻辑高电平转换为逻辑低电平时，第一个反相器接收信号并产生通过通道子系统的逻辑低电平信号。第二个反相器接收逻辑低电平信号并立即将其反相，将输出信号从逻辑高电平转换为逻辑低电平。逻辑低电平信号将上拉晶体管置于导通状态，以关断电路中的p器件。还公开了一种用于在两个部件之间转换电压信号的方法。

4. 发明授权

US6005412A AGP/DDR interfaces for full swing and reduced swing (SSTL) signals on an integrated circuit chip 失效
标题翻译： AGP / DDR接口，用于集成电路芯片上的全摆幅和降低摆幅（SSTL）信号
公开(公告)号：US6005412A
公开(公告)日：1999-12-21
申请号：US57047
申请日：1998-04-08
申请人： Nalini Ranjan , Xiaoyi Guo
发明人： Nalini Ranjan , Xiaoyi Guo
IPC分类号： G06F3/00 , G06F1/10 , G06F1/12 , G06F13/38 , G06F13/40 , G06F13/42 , H01L21/822 , H01L27/04 , H03K19/0175
CPC分类号： G06F13/4077
摘要： An I/O interface includes latches, clocks, and conditioning circuits implemented in a custom physical layout to produce a reliable and flexible interface to high frequency busses running a plurality of protocols and signal specifications. Three clock trees are used to synchronize the buffering and conditioning of input/output signals before sending such signals to a pad or core. The clock trees are implemented via custom layouts to allow tight control of clock/strobe parameters (e.g., skew, duty cycle, rise/fall times). Two of the clock trees are local to the I/O interface and trigger a plurality of output latches configured on-the-fly to buffer output data signals from the core in asynchronous or synchronous mode. In the synchronous mode, a clock/strobe could be either edge-centered or window-strobe with respect to the data. The third clock tree distributes clock/strobes from an external source and is used to trigger a plurality of input latches configured on-the-fly to buffer input data from the pad in either a window-strobe mode or an edge-centered mode. The I/O interface also includes conditioning circuits that condition the I/O signals to be compliant with AGP/DDR protocols, as well as, full swing, reduced swing (SSTL), and TTL signal specifications.
摘要翻译： I / O接口包括在自定义物理布局中实现的锁存器，时钟和调理电路，以产生运行多个协议和信号规范的高频总线的可靠且灵活的接口。在将这样的信号发送到垫或核之前，使用三个时钟树来同步输入/输出信号的缓冲和调节。时钟树通过定制布局来实现，以便对时钟/频闪参数进行严格控制（例如，偏斜，占空比，上升/下降时间）。两个时钟树是本地I / O接口，并触发多个输出锁存器配置，以异步或同步模式从核心缓冲输出数据信号。在同步模式下，相对于数据，时钟/频闪可以是边缘居中或窗口选通。第三个时钟树从外部源分配时钟/频闪，并用于触发多个输入锁存器配置，以在窗口选通模式或边缘中心模式下缓冲来自焊盘的输入数据。 I / O接口还包括调节电路，使I / O信号符合AGP / DDR协议，以及全摆幅，降低摆幅（SSTL）和TTL信号规格。

5. 发明授权

US6040737A Output buffer circuit and method that compensate for operating conditions and manufacturing processes 失效
标题翻译：输出缓冲电路和补偿工艺条件和制造工艺的方法
公开(公告)号：US6040737A
公开(公告)日：2000-03-21
申请号：US5077
申请日：1998-01-09
申请人： Nalini Ranjan , Henry Yang
发明人： Nalini Ranjan , Henry Yang
IPC分类号： G05F3/24 , H03F1/30 , H03F3/345 , H03F3/45 , H03K19/003 , G05F1/10
CPC分类号： H03K19/00384
摘要： The present invention provides improved output buffers for use on IC Chips. These output buffers incorporate a compensation circuit for compensating the performance characteristics of transistors included in the output buffers. The compensation circuit determines whether the output buffer is operating at a desired slew-rate. In response to this determination, the compensation circuit supplies a compensation voltage or voltages. The compensation voltages control a variable quantity of power delivered by a voltage controlled power source (VCPS). By increasing or reducing this power, the slew-rate of the output buffers are respectively increased or reduced. The compensation voltages maintain this slew-rate within narrow tolerances. This allows the improved output buffers of the present invention to meet very narrow input tolerances of circuitry coupled to receive signals from the IC Chip. The compensation circuit of the present invention is also beneficial for compensating various circuitry on an IC Chip, such as amplifier designs using constant current or power sources.
摘要翻译：本发明提供了用于IC芯片的改进的输出缓冲器。这些输出缓冲器包括用于补偿包括在输出缓冲器中的晶体管的性能特性的补偿电路。补偿电路确定输出缓冲器是否以所需的转换速率运行。响应于该确定，补偿电路提供补偿电压或电压。补偿电压控制由电压控制电源（VCPS）传递的可变功率量。通过增加或减少此功率，输出缓冲器的转换速率分别增加或减少。补偿电压在窄公差范围内保持该转换速率。这允许本发明的改进的输出缓冲器满足耦合到从IC芯片接收信号的电路的非常窄的输入容限。本发明的补偿电路对于补偿IC芯片上的各种电路，例如使用恒定电流或电源的放大器设计也是有益的。

6. 发明授权

US5862390A Mixed voltage, multi-rail, high drive, low noise, adjustable slew rate input/output buffer 失效
标题翻译：混合电压，多轨，高驱动，低噪声，可调压摆率输入/输出缓冲器
公开(公告)号：US5862390A
公开(公告)日：1999-01-19
申请号：US616835
申请日：1996-03-15
申请人： Nalini Ranjan
发明人： Nalini Ranjan
IPC分类号： H03K19/003 , G06K1/26 , H03K19/0175
CPC分类号： H03K19/00361
摘要： A universal input/output buffer uses all digital-type components, can be included on an integrated circuit chip and operates in a mixed voltage, multi-rail, power supply environment. The input/output buffer includes a multi-stage driver section and a sequencing section. Several types of sequencing techniques are used to control a plurality of driver stages and provide a combination of multiple firing schemes. In addition, other control techniques are employed such as full and partial feedback, sequential turn on/turn off of driver stages, and controlled introduction of a small amount of "crow bar" current.
摘要翻译：通用输入/输出缓冲器使用所有数字型组件，可以包含在集成电路芯片上，并在混合电压，多轨，电源环境中工作。输入/输出缓冲器包括多级驱动器部分和排序部分。使用几种类型的测序技术来控制多个驱动器级并提供多个点火方案的组合。此外，采用其他控制技术，例如全部和部分反馈，顺序打开/关闭驱动器级，以及控制引入少量的“撬棒”电流。

7. 发明授权

US06393600B1 Skew-independent memory architecture 有权
标题翻译：独立的内存架构
公开(公告)号：US06393600B1
公开(公告)日：2002-05-21
申请号：US09320191
申请日：1999-05-26
申请人： Sarathy Sribhashyam , David Hoff , Nalini Ranjan
发明人： Sarathy Sribhashyam , David Hoff , Nalini Ranjan
IPC分类号： G06F1750
CPC分类号： G11C8/08 , G11C7/22 , G11C8/18 , G11C2207/104
摘要： A word line block, a data block and at least one memory cell form a memory architecture and impose no special timing requirements to handle the synchronization of the outputs of the word line block with the data block. Further, the word line block contains a transmitting transistor and the data block contains a functionally similar transmitting transistor. These transmitting transistors responsive to a write enable signal and a clock signal synchronize a selection signal supplied to the memory cell when data is also supplied to the memory cell. Furthermore, a place in route tool can automatically place and route the word line block, the data block and the at least one memory cell based on chip requirements. Also, with the clock signal proximate the output of the word line block and data block, the place and route tool is able to automatically place and route the blocks and the at least one memory cell to compensate for any calculated interconnection delays. Moreover, since the word line block, the data block, and the at least one memory cell are separate blocks, flexibility is provided in the placement of the blocks as each block requires a reduced amount of layout space as compared to all three blocks together. Also provided is a process using synthesis method for creating a digital electronic circuit with the memory architecture including the word line block, the data block, and the at least one memory cell.
摘要翻译：字线块，数据块和至少一个存储器单元形成存储器架构，并且不施加特殊的时序要求来处理字线块与数据块的输出的同步。此外，字线块包含发射晶体管，并且数据块包含功能相似的发射晶体管。当数据也被提供给存储单元时，这些发送晶体管响应于写使能信号和时钟信号使提供给存储单元的选择信号同步。此外，路由工具中的位置可以根据芯片要求自动放置和布线字线块，数据块和至少一个存储单元。而且，由于时钟信号接近于字线块和数据块的输出，所以位置和路由工具能够自动地放置和布线块和至少一个存储器单元以补偿任何计算的互连延迟。此外，由于字线块，数据块和至少一个存储器单元是分离的块，所以在块的放置中提供了灵活性，因为与所有三个块相比，每个块需要减少的布局空间量。还提供了一种使用具有包括字线块，数据块和至少一个存储单元的存储架构来创建数字电子电路的合成方法的过程。

8. 发明授权

US06208167B1 Voltage tolerant buffer 失效
标题翻译：耐压缓冲器
公开(公告)号：US06208167B1
公开(公告)日：2001-03-27
申请号：US08974073
申请日：1997-11-19
申请人： Nalini Ranjan , Sarathy Sribhashyam
发明人： Nalini Ranjan , Sarathy Sribhashyam
IPC分类号： H03K190175
CPC分类号： H03K3/356113 , H03K19/018521
摘要： The present invention provides a buffer for coupling circuitry operating at a low voltage to circuitry operating a high voltage, and vice versa. The buffer outputs signals in a range between the low voltage and a ground voltage lower than the low voltage, and maintains appropriate bias of a semiconductor junction in the buffer using the high voltage. For example, the high voltage can be applied to the body of an output stage pull-up PFET of the buffer to maintain reverse bias between the body and drain of the PFET even when signals at the high voltage are placed on the drain of the PFET by other circuitry. Some embodiments of the present invention include a voltage translator to translate signals output from circuitry operating at the low voltage into a control signal at either the ground voltage or the high voltage. The high voltage of the control signal is beneficial for turning OFF an output stage transistor of the buffer even in the presence of signals at the high voltage on an output of the buffer. The roles of the low and high voltage can also be reversed, for example, by using a ground voltage higher than the high voltage.
摘要翻译：本发明提供一种缓冲器，用于将在低电压操作的电路耦合到操作高电压的电路，反之亦然。缓冲器在低电压和低于低电压的接地电压之间的范围内输出信号，并且使用高电压保持缓冲器中的半导体结的适当偏置。例如，高电压可以施加到缓冲器的输出级上拉PFET的主体，以保持PFET的体和漏极之间的反向偏置，即使高电压信号被放置在PFET的漏极上通过其他电路。本发明的一些实施例包括电压转换器，用于将在低电压下操作的电路输出的信号转换为接地电压或高电压的控制信号。控制信号的高电压即使在存在缓冲器的输出上的高电压的信号的情况下也有利于关闭缓冲器的输出级晶体管。例如，通过使用高于高电压的接地电压，也可以反转低电压和高电压的作用。

9. 发明授权

US5852568A System and method for a fast carry/sum select adder 失效
标题翻译：用于快速进位/和选择加法器的系统和方法
公开(公告)号：US5852568A
公开(公告)日：1998-12-22
申请号：US788391
申请日：1997-01-27
申请人： Nalini Ranjan
发明人： Nalini Ranjan
IPC分类号： G06F7/507 , G06F7/50 , G06F7/506 , G06F7/508
CPC分类号： G06F7/507
摘要： An adder system includes at least one adder block subsystem. Each adder block subsystem includes a pair of input signal lines, an adder circuit block having a conditional sum-select and a conditional carry-select, a sum-high line, a sum-low line, a carry-high line, carry-low line, a sum selection switch, a carry selection switch, a carry forward line, and an output signal line. The input lines are individual bit lines that are paired together from the least significant bit to the most significant bit. Within the adder circuit block, pairs of the input bit lines are coupled to the conditional sum-select and the conditional carry-select. The conditional sum-select is coupled to the sum-high and sum-low lines and the conditional carry-select is coupled to the carry-high and carry-low line. The sum selection switch selectively couples the output signal line to the sum-high or the sum-low line. The carry selection switch selectively couples the carry-high or carry-low line to the carry forward line that is coupled to the next adder subsystem which is structured similarly. The carry signal of the adder system is determined through the conditional carry selects of the adder circuit blocks. Each conditional carry-select includes logic OR and logic AND subcircuits to which each of the pairs of input bit lines is respectively coupled. The outputs of the logic OR and logic AND subcircuits are coupled to one or more line multiplexes to selectively produce a logic high or logic low signal that serves as the individual carry bit signals for the carry signal. A method for an adder system is also disclosed.
摘要翻译：加法器系统包括至少一个加法器块子系统。每个加法器块子系统包括一对输入信号线，具有条件和选择和条件进位选择的加法器电路块，和和线，和和线，进位高线，进位电位线，和选择开关，进位选择开关，进位线和输出信号线。输入线是从最低有效位到最高有效位配对的单独位线。在加法器电路块内，输入位线对耦合到条件求和和条件进位选择。条件求和选择被耦合到和高和和线，并且条件进位选择被耦合到进位高和进位低的线。总和选择开关将输出信号线选择性地耦合到和高或低和线。进位选择开关选择性地将进位高或进位低的线耦合到耦合到类似地被构造的下一个加法器子系统的进位线。加法器系统的进位信号通过加法器电路块的条件进位选择来确定。每个条件进位选择包括分别耦合输入位线对中的每一对的逻辑OR和逻辑与子电路。逻辑和逻辑与子电路的输出耦合到一个或多个线路多路复用，以选择性地产生用作进位信号的各个进位位信号的逻辑高或逻辑低电平信号。还公开了一种加法器系统的方法。

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