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1. 发明授权

US6005432A Voltage level shift system and method 失效
标题翻译：电压电平转换系统及方法
公开(公告)号：US6005432A
公开(公告)日：1999-12-21
申请号：US53555
申请日：1998-04-01
申请人： Xiaoyi Guo , Nalini Ranjan
发明人： Xiaoyi Guo , Nalini Ranjan
IPC分类号： H03K19/0185 , G06F5/00
CPC分类号： H03K19/018521
摘要： A voltage level shift system transitions a voltage signal between two components and includes a first inverter, a signal pass subsystem, a pull-up transistor, a second inverter, and a third inverter. The first inverter is coupled to the signal pass subsystem. The signal pass subsystem is coupled to the pull-up transistor, the second inverter, and the third inverter. The signal pass subsystem includes a first passgate and a second passgate. When an input voltage transitions from a logic low to a logic high, the first inverter inverts the logic high input signal to a logic low and passes this signal through the passgate subsystem. The second inverter receives the logic low signal and immediately inverts it to transition the output signal from a low logic to a logic high. The logic high output signal, turns off the pull-up transistor. When the input signal transitions from a logic high to a logic low, the first inverter receives the signal and generates a logic low signal that passes through the passgate subsystem. The second inverter receives the logic low signal and immediately inverts it to transition the output signal from a logic high to a logic low. The logic low signal places the pull-up transistor in an on state to turn off the p-device in the circuit. A method for transitioning a voltage signal between two components is also disclosed.
摘要翻译：电压电平移位系统转换两个部件之间的电压信号，并且包括第一反相器，信号传递子系统，上拉晶体管，第二反相器和第三反相器。第一个反相器耦合到信号传递子系统。信号传递子系统耦合到上拉晶体管，第二反相器和第三反相器。信号传递子系统包括第一传递门和第二传递门。当输入电压从逻辑低电平转换为逻辑高电平时，第一个反相器将逻辑高输入信号反相为逻辑低电平，并将该信号传递通过门电路子系统。第二个反相器接收逻辑低电平信号，并立即将其反相，将输出信号从低逻辑转换为逻辑高电平。逻辑高输出信号，关闭上拉晶体管。当输入信号从逻辑高电平转换为逻辑低电平时，第一个反相器接收信号并产生通过通道子系统的逻辑低电平信号。第二个反相器接收逻辑低电平信号并立即将其反相，将输出信号从逻辑高电平转换为逻辑低电平。逻辑低电平信号将上拉晶体管置于导通状态，以关断电路中的p器件。还公开了一种用于在两个部件之间转换电压信号的方法。

2. 发明授权

US6005412A AGP/DDR interfaces for full swing and reduced swing (SSTL) signals on an integrated circuit chip 失效
标题翻译： AGP / DDR接口，用于集成电路芯片上的全摆幅和降低摆幅（SSTL）信号
公开(公告)号：US6005412A
公开(公告)日：1999-12-21
申请号：US57047
申请日：1998-04-08
申请人： Nalini Ranjan , Xiaoyi Guo
发明人： Nalini Ranjan , Xiaoyi Guo
IPC分类号： G06F3/00 , G06F1/10 , G06F1/12 , G06F13/38 , G06F13/40 , G06F13/42 , H01L21/822 , H01L27/04 , H03K19/0175
CPC分类号： G06F13/4077
摘要： An I/O interface includes latches, clocks, and conditioning circuits implemented in a custom physical layout to produce a reliable and flexible interface to high frequency busses running a plurality of protocols and signal specifications. Three clock trees are used to synchronize the buffering and conditioning of input/output signals before sending such signals to a pad or core. The clock trees are implemented via custom layouts to allow tight control of clock/strobe parameters (e.g., skew, duty cycle, rise/fall times). Two of the clock trees are local to the I/O interface and trigger a plurality of output latches configured on-the-fly to buffer output data signals from the core in asynchronous or synchronous mode. In the synchronous mode, a clock/strobe could be either edge-centered or window-strobe with respect to the data. The third clock tree distributes clock/strobes from an external source and is used to trigger a plurality of input latches configured on-the-fly to buffer input data from the pad in either a window-strobe mode or an edge-centered mode. The I/O interface also includes conditioning circuits that condition the I/O signals to be compliant with AGP/DDR protocols, as well as, full swing, reduced swing (SSTL), and TTL signal specifications.
摘要翻译： I / O接口包括在自定义物理布局中实现的锁存器，时钟和调理电路，以产生运行多个协议和信号规范的高频总线的可靠且灵活的接口。在将这样的信号发送到垫或核之前，使用三个时钟树来同步输入/输出信号的缓冲和调节。时钟树通过定制布局来实现，以便对时钟/频闪参数进行严格控制（例如，偏斜，占空比，上升/下降时间）。两个时钟树是本地I / O接口，并触发多个输出锁存器配置，以异步或同步模式从核心缓冲输出数据信号。在同步模式下，相对于数据，时钟/频闪可以是边缘居中或窗口选通。第三个时钟树从外部源分配时钟/频闪，并用于触发多个输入锁存器配置，以在窗口选通模式或边缘中心模式下缓冲来自焊盘的输入数据。 I / O接口还包括调节电路，使I / O信号符合AGP / DDR协议，以及全摆幅，降低摆幅（SSTL）和TTL信号规格。

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