专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06393600B1 Skew-independent memory architecture 有权
标题翻译：独立的内存架构
公开(公告)号：US06393600B1
公开(公告)日：2002-05-21
申请号：US09320191
申请日：1999-05-26
申请人： Sarathy Sribhashyam , David Hoff , Nalini Ranjan
发明人： Sarathy Sribhashyam , David Hoff , Nalini Ranjan
IPC分类号： G06F1750
CPC分类号： G11C8/08 , G11C7/22 , G11C8/18 , G11C2207/104
摘要： A word line block, a data block and at least one memory cell form a memory architecture and impose no special timing requirements to handle the synchronization of the outputs of the word line block with the data block. Further, the word line block contains a transmitting transistor and the data block contains a functionally similar transmitting transistor. These transmitting transistors responsive to a write enable signal and a clock signal synchronize a selection signal supplied to the memory cell when data is also supplied to the memory cell. Furthermore, a place in route tool can automatically place and route the word line block, the data block and the at least one memory cell based on chip requirements. Also, with the clock signal proximate the output of the word line block and data block, the place and route tool is able to automatically place and route the blocks and the at least one memory cell to compensate for any calculated interconnection delays. Moreover, since the word line block, the data block, and the at least one memory cell are separate blocks, flexibility is provided in the placement of the blocks as each block requires a reduced amount of layout space as compared to all three blocks together. Also provided is a process using synthesis method for creating a digital electronic circuit with the memory architecture including the word line block, the data block, and the at least one memory cell.
摘要翻译：字线块，数据块和至少一个存储器单元形成存储器架构，并且不施加特殊的时序要求来处理字线块与数据块的输出的同步。此外，字线块包含发射晶体管，并且数据块包含功能相似的发射晶体管。当数据也被提供给存储单元时，这些发送晶体管响应于写使能信号和时钟信号使提供给存储单元的选择信号同步。此外，路由工具中的位置可以根据芯片要求自动放置和布线字线块，数据块和至少一个存储单元。而且，由于时钟信号接近于字线块和数据块的输出，所以位置和路由工具能够自动地放置和布线块和至少一个存储器单元以补偿任何计算的互连延迟。此外，由于字线块，数据块和至少一个存储器单元是分离的块，所以在块的放置中提供了灵活性，因为与所有三个块相比，每个块需要减少的布局空间量。还提供了一种使用具有包括字线块，数据块和至少一个存储单元的存储架构来创建数字电子电路的合成方法的过程。

2. 发明授权

US06208167B1 Voltage tolerant buffer 失效
标题翻译：耐压缓冲器
公开(公告)号：US06208167B1
公开(公告)日：2001-03-27
申请号：US08974073
申请日：1997-11-19
申请人： Nalini Ranjan , Sarathy Sribhashyam
发明人： Nalini Ranjan , Sarathy Sribhashyam
IPC分类号： H03K190175
CPC分类号： H03K3/356113 , H03K19/018521
摘要： The present invention provides a buffer for coupling circuitry operating at a low voltage to circuitry operating a high voltage, and vice versa. The buffer outputs signals in a range between the low voltage and a ground voltage lower than the low voltage, and maintains appropriate bias of a semiconductor junction in the buffer using the high voltage. For example, the high voltage can be applied to the body of an output stage pull-up PFET of the buffer to maintain reverse bias between the body and drain of the PFET even when signals at the high voltage are placed on the drain of the PFET by other circuitry. Some embodiments of the present invention include a voltage translator to translate signals output from circuitry operating at the low voltage into a control signal at either the ground voltage or the high voltage. The high voltage of the control signal is beneficial for turning OFF an output stage transistor of the buffer even in the presence of signals at the high voltage on an output of the buffer. The roles of the low and high voltage can also be reversed, for example, by using a ground voltage higher than the high voltage.
摘要翻译：本发明提供一种缓冲器，用于将在低电压操作的电路耦合到操作高电压的电路，反之亦然。缓冲器在低电压和低于低电压的接地电压之间的范围内输出信号，并且使用高电压保持缓冲器中的半导体结的适当偏置。例如，高电压可以施加到缓冲器的输出级上拉PFET的主体，以保持PFET的体和漏极之间的反向偏置，即使高电压信号被放置在PFET的漏极上通过其他电路。本发明的一些实施例包括电压转换器，用于将在低电压下操作的电路输出的信号转换为接地电压或高电压的控制信号。控制信号的高电压即使在存在缓冲器的输出上的高电压的信号的情况下也有利于关闭缓冲器的输出级晶体管。例如，通过使用高于高电压的接地电压，也可以反转低电压和高电压的作用。

3. 发明授权

US5973511A Voltage tolerant input/output buffer 有权
标题翻译：耐压输入/输出缓冲器
公开(公告)号：US5973511A
公开(公告)日：1999-10-26
申请号：US225650
申请日：1999-01-05
申请人： Yuwen Hsia , Sarathy Sribhashyam
发明人： Yuwen Hsia , Sarathy Sribhashyam
IPC分类号： H03K19/003 , H03K19/094 , H03K19/0185
CPC分类号： H03K19/00315 , H03K19/09429
摘要： A voltage tolerant input/output buffer comprises a current mirror, a voltage sensing and isolating circuit, an output pull-up transistor, and an output pull-down transistor. The output pull-up transistor preferably has its gate coupled to the voltage sensing and isolating circuit to receive signals from the lower voltage circuitry, its source coupled to the supply voltage for the lower operating voltage circuitry, and its drain provides the output for connection to the higher voltage circuitry. The voltage sensing and isolating circuit is coupled between the gate and the drain of the output pull-up transistor. The current mirror is coupled to ground and to the voltage sensing and isolating circuit. The output pull-down transistor has its drain coupled to the voltage sensing and isolating circuit, it source coupled to ground, and its gate coupled to receive pull down signals from the lower operating voltage circuit. The current mirror and the voltage sensing and isolating circuit are provided such that as the higher voltage circuit applies a high supply voltage to the drain of the pull-up output transistor, the pull-up output transistor is able to transition to a state at the supply voltage of the lower circuit and sink the current such that the buffer operates properly and correctly, unaffected by the application of the higher operating supply voltage to the drain of the pull-up transistor.
摘要翻译：电压容差输入/输出缓冲器包括电流镜，电压感测和隔离电路，输出上拉晶体管和输出下拉晶体管。输出上拉晶体管优选地具有耦合到电压感测和隔离电路的栅极，以接收来自较低电压电路的信号，其源极耦合到用于下部工作电压电路的电源电压，并且其漏极提供用于连接到较高的电压电路。电压感测和隔离电路耦合在输出上拉晶体管的栅极和漏极之间。电流镜耦合到地和电压感测和隔离电路。输出下拉晶体管的漏极耦合到电压感测和隔离电路，其源极耦合到地，并且其栅极被耦合以从下部工作电压电路接收下拉信号。提供电流镜和电压感测和隔离电路，使得当较高电压电路向上拉输出晶体管的漏极施加高电源电压时，上拉输出晶体管能够转变到电源电压下降，并使电流正常工作，使得缓冲器工作正常且不受高电压施加到上拉晶体管的漏极的影响。

4. 发明授权

US08732635B2 Apparatus and methods for power management in integrated circuits 有权
标题翻译：集成电路中电源管理的装置和方法
公开(公告)号：US08732635B2
公开(公告)日：2014-05-20
申请号：US12165665
申请日：2008-07-01
申请人： David Lewis , Christopher F. Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
发明人： David Lewis , Christopher F. Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
IPC分类号： G06F17/50 , G06F9/455 , H03K3/01 , G05F1/10
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
摘要翻译：可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。控制电路耦合到非易失性存储器和配置存储器。一组电压从控制电路的输出导出，并被应用于PLD内的电路。

5. 发明授权

US07317340B2 Glitch free reset circuit 有权
标题翻译：无毛刺复位电路
公开(公告)号：US07317340B2
公开(公告)日：2008-01-08
申请号：US11365068
申请日：2006-02-28
申请人： Sarathy Sribhashyam , David Hoff , Ken Ming Li
发明人： Sarathy Sribhashyam , David Hoff , Ken Ming Li
IPC分类号： G01R29/02 , H03K9/08
CPC分类号： H03K5/1252
摘要： An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will be in the same state. An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will have a state similar to the state of the incoming signal, and when the incoming signal and the delayed incoming signal are not in the same state, the output signal will have a state similar to a previously sampled state of the incoming signal.
摘要翻译：一种用于补偿在集成电路中应用的复位信号中的毛刺发生的装置，包括：能够处理输入信号的逻辑级和作为输入信号的延迟版本的延迟输入信号，逻辑级能够产生输出信号，使得当输入信号和延迟输入信号处于相同状态时，输出信号将处于相同状态。一种用于补偿在集成电路中应用的复位信号中的毛刺发生的装置，包括：能够处理输入信号的逻辑级和作为输入信号的延迟版本的延迟输入信号，逻辑级能够产生输出信号，使得当输入信号和延迟的输入信号处于相同状态时，输出信号将具有与输入信号的状态相似的状态，并且当输入信号和延迟的输入信号不在相同的状态，输出信号将具有类似于输入信号的先前采样状态的状态。

6. 发明申请

US20070040576A1 Apparatus and methods for power management in integrated circuits 有权
标题翻译：集成电路中电源管理的装置和方法
公开(公告)号：US20070040576A1
公开(公告)日：2007-02-22
申请号：US11316390
申请日：2005-12-22
申请人： David Lewis , Christopher Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Wong , Andy Lee
发明人： David Lewis , Christopher Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Wong , Andy Lee
IPC分类号： H03K19/177
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
摘要翻译：可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。控制电路耦合到非易失性存储器和配置存储器。一组电压从控制电路的输出导出，并被应用于PLD内的电路。

7. 发明授权

US07405589B2 Apparatus and methods for power management in integrated circuits 有权
标题翻译：集成电路中电源管理的装置和方法
公开(公告)号：US07405589B2
公开(公告)日：2008-07-29
申请号：US11316390
申请日：2005-12-22
申请人： David Lewis , Christopher F. Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
发明人： David Lewis , Christopher F. Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
IPC分类号： H03K19/173
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
摘要翻译：可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。控制电路耦合到非易失性存储器和配置存储器。一组电压从控制电路的输出导出，并被应用于PLD内的电路。

8. 发明授权

US5907249A Voltage tolerant input/output buffer 失效
公开(公告)号：US5907249A
公开(公告)日：1999-05-25
申请号：US801002
申请日：1997-02-19
申请人： Yuwen Hsia , Sarathy Sribhashyam
发明人： Yuwen Hsia , Sarathy Sribhashyam
IPC分类号： H03K19/003 , H03K19/094 , H03K19/0185
CPC分类号： H03K19/00315 , H03K19/09429
摘要： A voltage tolerant input/output buffer comprises a current mirror, a voltage sensing and isolating circuit, an output pull-up transistor, and an output pull-down transistor. The output pull-up transistor preferably has its gate coupled to the voltage sensing and isolating circuit to receive signals from the lower voltage circuitry, its source coupled to the supply voltage for the lower operating voltage circuitry, and its drain provides the output for connection to the higher voltage circuitry. The voltage sensing and isolating circuit is coupled between the gate and the drain of the output pull-up transistor. The current mirror is coupled to ground and to the voltage sensing and isolating circuit. The output pull-down transistor has its drain coupled to the voltage sensing and isolating circuit, it source coupled to ground, and its gate coupled to receive pull down signals from the lower operating voltage circuit. The current mirror and the voltage sensing and isolating circuit are provided such that as the higher voltage circuit applies a high supply voltage to the drain of the pull-up output transistor, the pull-up output transistor is able to transition to a state at the supply voltage of the lower circuit and sink the current such that the buffer operates properly and correctly, unaffected by the application of the higher operating supply voltage to the drain of the pull-up transistor.

9. 发明申请

US20080263481A1 APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS 有权
标题翻译：集成电路中电源管理的装置和方法
公开(公告)号：US20080263481A1
公开(公告)日：2008-10-23
申请号：US12165665
申请日：2008-07-01
申请人： David Lewis , Christopher F. Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
发明人： David Lewis , Christopher F. Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
摘要翻译：可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。控制电路耦合到非易失性存储器和配置存储器。一组电压从控制电路的输出导出，并被应用于PLD内的电路。

10. 发明申请

US20060145727A1 Glitch free reset circuit 有权
标题翻译：无毛刺复位电路
公开(公告)号：US20060145727A1
公开(公告)日：2006-07-06
申请号：US11365068
申请日：2006-02-28
申请人： Sarathy Sribhashyam , David Hoff , Ken Li
发明人： Sarathy Sribhashyam , David Hoff , Ken Li
IPC分类号： G01R29/02
CPC分类号： H03K5/1252
摘要： An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will be in the same state. An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will have a state similar to the state of the incoming signal, and when the incoming signal and the delayed incoming signal are not in the same state, the output signal will have a state similar to a previously sampled state of the incoming signal.
摘要翻译：一种用于补偿在集成电路中应用的复位信号中的毛刺发生的装置，包括：能够处理输入信号的逻辑级和作为输入信号的延迟版本的延迟输入信号，逻辑级能够产生输出信号，使得当输入信号和延迟的输入信号处于相同状态时，输出信号将处于相同的状态。一种用于补偿在集成电路中应用的复位信号中的毛刺发生的装置，包括：能够处理输入信号的逻辑级和作为输入信号的延迟版本的延迟输入信号，逻辑级能够产生输出信号，使得当输入信号和延迟的输入信号处于相同状态时，输出信号将具有与输入信号的状态相似的状态，并且当输入信号和延迟的输入信号不在相同的状态，输出信号将具有类似于输入信号的先前采样状态的状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式