专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5644729A Bidirectional data buffer for a bus-to-bus interface unit in a computer system 失效
标题翻译：计算机系统中总线到总线接口单元的双向数据缓冲器
公开(公告)号：US5644729A
公开(公告)日：1997-07-01
申请号：US282159
申请日：1994-07-28
申请人： Nader Amini , Bechara Fouad Boury , Sherwood Brannon , Richard Louis Horne , Terence Joseph Lohman
发明人： Nader Amini , Bechara Fouad Boury , Sherwood Brannon , Richard Louis Horne , Terence Joseph Lohman
IPC分类号： G06F13/28 , G06F13/16 , G06F13/40 , G06F13/00
CPC分类号： G06F13/1673 , G06F13/4059
摘要： A method and system are provided for controlling data transfer between a system memory connected to a system bus and at least one input/output (I/O) device connected to an I/O bus in a computer system. The system bus is coupled to the I/O bus by a bus interface unit comprising a first pair of buffers connected in series between the I/O bus and the system bus, and a second pair of buffers connected in series between the I/O bus and the system bus and in parallel with the first pair of buffers. Each of the buffers in each of the pairs is used for bidirectional data transfer between the system bus and the I/O bus.
摘要翻译：提供了一种用于控制连接到系统总线的系统存储器与连接到计算机系统中的I / O总线的至少一个输入/输出（I / O）设备之间的数据传输的方法和系统。系统总线通过总线接口单元耦合到I / O总线，总线接口单元包括串联连接在I / O总线和系统总线之间的第一对缓冲器，以及串联连接在I / O之间的第二对缓冲器总线和系统总线，并与第一对缓冲器并联。每对中的每个缓冲区用于系统总线和I / O总线之间的双向数据传输。

2. 发明授权

US5673414A Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device 失效
标题翻译：侦听I / O总线，并使处理器缓存无效，从而在另一个I / O设备中的一个I / O设备和可高速缓存的存储器之间进行存储器数据传输
公开(公告)号：US5673414A
公开(公告)日：1997-09-30
申请号：US327136
申请日：1994-10-21
申请人： Nader Amini , Bechara Fouad Boury , Sherwood Brannon , Richard Louis Horne
发明人： Nader Amini , Bechara Fouad Boury , Sherwood Brannon , Richard Louis Horne
IPC分类号： G06F12/08 , G06F13/00 , G06F13/36 , G06F13/40
CPC分类号： G06F12/0835
摘要： In a computer system that contains an input output (I/O) bus connecting to I/O devices, a central processing unit (CPU), a CPU cache memory, a system memory not directly accessible via the I/O bus, and a system bus used for conducting data transfers between the I/O bus and both the CPU cache and system memory, a method and apparatus are provided to allow addressable memory locations in both the system memory and I/O devices coupled to the I/O bus to be cacheable in the CPU cache. The I/O bus supports data transfers between pairs of I/O devices, as well as data transfers between individual I/O devices and the system which presents a problem of maintaining coherency in the CPU cache when data is written by one I/O device to a cacheable memory location in another I/O device. The present solution employs a snoop/data invalidation function at the system interface to the I/O bus to determine when a memory location in an I/O device coupled to the I/O bus is being written to by another I/O device coupled to the I/O bus. If such a write is taking place, it is then determined if the address of the location being written is in an address range predesignated as cacheable; if so, then the CPU cache controller or other device controlling the CPU cache is notified that memory at a cacheable location in an I/O device has been overwritten.
摘要翻译：在包含连接到I / O设备的输入输出（I / O）总线的计算机系统中，中央处理单元（CPU），CPU高速缓冲存储器，不能通过I / O总线直接访问的系统存储器和用于在I / O总线与CPU高速缓存和系统存储器之间进行数据传输的系统总线，提供了一种方法和装置，以允许耦合到I / O总线的系统存储器和I / O设备中的可寻址存储器位置可缓存在CPU缓存中。 I / O总线支持I / O设备之间的数据传输，以及单个I / O设备与系统之间的数据传输，当数据由一个I / O写入时，会出现维护CPU高速缓存中的一致性问题设备到另一个I / O设备中的可缓存存储器位置。本解决方案在I / O总线的系统接口处采用窥探/数据无效功能，以确定耦合到I / O总线的I / O设备中的存储器位置何时被另一个耦合的I / O设备写入到I / O总线。如果发生这样的写入，则确定正在写入的位置的地址是否在预先指定为可缓存的地址范围内; 如果是这样，则CPU缓存控制器或控制CPU高速缓存的其他设备被通知，I / O设备中可缓存位置的存储器已被覆盖。

3. 发明授权

US5966728A Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device 失效
标题翻译：用于窥探数据写入到扩展存储器设备中的可缓存存储器位置的计算机系统和方法
公开(公告)号：US5966728A
公开(公告)日：1999-10-12
申请号：US490648
申请日：1995-06-15
申请人： Nader Amini , Bechara Fouad Boury , Sherwood Brannon , Richard Louis Horne
发明人： Nader Amini , Bechara Fouad Boury , Sherwood Brannon , Richard Louis Horne
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0835
摘要： A computer system and method allow memory locations in both system memory and expansion memory devices coupled to an input/output (I/O) bus to be cacheable in a central processing unit (CPU) cache. The computer system contains an I/O bus connected to I/O devices and an expansion bus connected to expansion memory devices, a system memory not accessible via the I/O bus or expansion bus, and the system bus used for conducting data transfers between the I/O bus and both the CPU cache and system memory. The I/O bus supports data transfers between pairs of I/O devices, and I/O devices and expansion memory devices on the expansion bus, as well as data transfers between individual I/O devices and the system, which presents a problem of maintaining coherency in the CPU cache when data is written by one I/O device or expansion memory device to a cacheable memory location in another I/O device or expansion memory device. The computer system employs a snoop/data invalidation function at the system interface to the I/O bus to determine when a memory location in an expansion memory device coupled to the expansion bus is being written to by another expansion memory device coupled to the expansion bus or an I/O device coupled to the I/O bus. If such a write is taking place, it is then determined if the address of the location being written is in and address range predesignated as cacheable; if so, then the CPU cache controller or other device controlling the CPU cache is notified that memory at a cacheable location in an expansion memory device has been overwritten.
摘要翻译：计算机系统和方法允许耦合到输入/输出（I / O）总线的系统存储器和扩展存储器设备中的存储器位置在中央处理单元（CPU）高速缓存中可高速缓存。计算机系统包含连接到I / O设备的I / O总线和连接到扩展存储器设备的扩展总线，不能通过I / O总线或扩展总线访问的系统存储器，以及用于进行数据传输的系统总线 I / O总线以及CPU缓存和系统内存。 I / O总线支持I / O设备之间的数据传输，扩展总线上的I / O设备和扩展存储设备之间的数据传输，以及各个I / O设备与系统之间的数据传输，当数据由一个I / O设备或扩展存储器设备写入到另一个I / O设备或扩展存储器设备中的可高速缓存存储器位置时，保持CPU高速缓存中的一致性。计算机系统在I / O总线的系统接口处采用窥探/数据无效功能，以确定耦合到扩展总线的扩展存储器件中的存储器位置何时被耦合到扩展总线的另一个扩展存储器件写入或耦合到I / O总线的I / O设备。如果发生这样的写入，则确定正在写入的位置的地址是否在预先指定为可缓存的地址范围内; 如果是这样，则CPU缓存控制器或控制CPU高速缓存的其他设备被通知，扩展存储器设备中的可缓存位置处的存储器已被覆盖。

4. 发明授权

US5333274A Error detection and recovery in a DMA controller 失效
标题翻译： DMA控制器中的错误检测和恢复
公开(公告)号：US5333274A
公开(公告)日：1994-07-26
申请号：US778040
申请日：1991-10-15
申请人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Richard G. Hofmann , Terence J. Lohman
发明人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Richard G. Hofmann , Terence J. Lohman
IPC分类号： G06F13/00 , G06F11/00 , G06F11/14 , G06F11/20 , G06F13/28
CPC分类号： G06F13/28 , G06F11/00 , G06F11/0751 , G06F11/0757 , G06F11/0763 , G06F11/1402
摘要： A DMA controller with error circuitry which detects DMA error conditions is disclosed. The error circuitry causes the DMA controller to perform completion tasks before terminating a DMA transfer, advantageously providing a DMA controller which may exit gracefully upon detection of an error condition with the potential of error recovery.
摘要翻译：公开了一种具有检测DMA错误状况的错误电路的DMA控制器。错误电路使得DMA控制器在终止DMA传输之前执行完成任务，有利地提供了一个DMA控制器，它可以在检测到具有错误恢复潜力的错误状况时正常地退出。

5. 发明授权

US5313627A Parity error detection and recovery 失效
标题翻译：奇偶校验错误检测和恢复
公开(公告)号：US5313627A
公开(公告)日：1994-05-17
申请号：US816184
申请日：1992-01-02
申请人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Richard L. Horne
发明人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Richard L. Horne
IPC分类号： G06F11/07 , G06F11/10 , G06F11/22 , G06F13/00 , G06F11/00
CPC分类号： G06F11/10 , G06F11/0745 , G06F11/079 , G06F11/0793 , G06F11/2205
摘要： In a computer system having a CPU and several buses which includes a system bus and an I/O bus, parity error can occur when data is being written between the I/O bus and the system bus. This invention provides a technique for detecting whether a parity error has occurred on data being written between the system bus and the I/O bus. If a parity error is detected, the address at which such error occurred is stored and then sent on to the system bus to the CPU.
摘要翻译：在具有CPU和包括系统总线和I / O总线的若干总线的计算机系统中，当数据被写入I / O总线和系统总线之间时，可能会发生奇偶校验错误。本发明提供一种用于检测在系统总线和I / O总线之间写入的数据是否发生奇偶校验错误的技术。如果检测到奇偶校验错误，则存储发生这种错误的地址，然后发送到CPU的系统总线。

6. 发明授权

US5544346A System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus 失效
标题翻译：系统具有总线接口单元，用于在系统资源设备已经获得总线控制之后超越正常的仲裁方案
公开(公告)号：US5544346A
公开(公告)日：1996-08-06
申请号：US353165
申请日：1994-12-09
申请人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Richard L. Horne , Terence J. Lohman
发明人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Richard L. Horne , Terence J. Lohman
IPC分类号： G06F13/36 , G06F13/16 , G06F13/00 , G06F13/40
CPC分类号： G06F13/1605
摘要： An information handling systems capable of transferring data among various system resource devices such as input/output (I/O) devices and a system memory includes a first bus coupled to the system memory, a second bus coupled to the system resource devices, and a bus interface unit (BIU) coupled between the first bus and the second bus. Each of the system resource devices is capable of controlling the second bus after arbitrating therefor. The BIU includes a buffer for temporary storage of data being transferred between the first bus and the second bus, and control logic for generating a lock control signal, after one of the system resource devices has gained control of the second bus by arbitration, to gain control of the first bus to prevent other system resource devices from accessing the first bus. The control signal is dynamically generated by the BIU based on programmable conditions relating to the data transfer, thus optimizing data transfers between the first bus and the second bus. The control signal may act as an override to the normal memory controller arbitration scheme to prioritize access of the system resource devices to the system memory.
摘要翻译：能够在诸如输入/输出（I / O）设备和系统存储器的各种系统资源设备之间传送数据的信息处理系统包括耦合到系统存储器的第一总线，耦合到系统资源设备的第二总线，以及总线接口单元（BIU），耦合在第一总线和第二总线之间。每个系统资源设备在对其进行仲裁之后能够控制第二总线。 BIU包括用于临时存储在第一总线和第二总线之间传输的数据的缓冲器，以及用于在系统资源设备之一通过仲裁获得第二总线的控制之后产生锁定控制信号的控制逻辑，以获得控制第一总线以防止其他系统资源设备访问第一总线。基于与数据传输相关的可编程条件，BIU动态地产生控制信号，从而优化第一总线与第二总线之间的数据传输。控制信号可以作为对正常存储器控制器仲裁方案的覆盖，以优先考虑系统资源设备对系统存储器的访问。

7. 发明授权

US5551009A Expandable high performance FIFO design which includes memory cells having respective cell multiplexors 失效
标题翻译：可扩展的高性能FIFO设计，其包括具有相应的单元复用器的存储单元
公开(公告)号：US5551009A
公开(公告)日：1996-08-27
申请号：US134504
申请日：1993-10-12
申请人： Nader Amini , Bechara E. Boury , Sherwood Brannon , Terence J. Lohman
发明人： Nader Amini , Bechara E. Boury , Sherwood Brannon , Terence J. Lohman
IPC分类号： G06F12/00 , G06F5/06 , G11C7/00 , G06F13/00 , G06F13/04
CPC分类号： G06F5/065
摘要： An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided with an arrangement of self contained FIFO cells, each cell containing its own input multiplexer and control circuitry.
摘要翻译：公开了具有输入和输出转向电路以及内部移位能力的单元的布置，其有利地提供可以连续的时钟周期写入和读取的第一进/出（FIFO）寄存器电路。 FIFO寄存器电路具有自包含FIFO单元的布置，每个单元包含其自己的输入多路复用器和控制电路。

8. 发明授权

US5548786A Dynamic bus sizing of DMA transfers 失效
标题翻译： DMA传输的动态总线大小
公开(公告)号：US5548786A
公开(公告)日：1996-08-20
申请号：US224123
申请日：1994-04-06
申请人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Ian A. Concilio , Richard G. Hofmann , Terence J. Lohman
发明人： Nader Amini , Bechara F. Boury , Sherwood Brannon , Ian A. Concilio , Richard G. Hofmann , Terence J. Lohman
IPC分类号： G06F13/28 , G06F13/00 , G06F13/40
CPC分类号： G06F13/28
摘要： A DMA controller is provided for transferring data between source and destination devices over an I/O bus. The DMA control circuit includes a bus interface unit for providing a bus size information at the beginning of each consecutive bus cycle and a look ahead responsive to the bus size information for providing a bus size control signal. A DMA control circuit responsive to the bus size control signal controls the bus width during contiguous transfer cycles. By dynamically adjusting the DMA control circuit, back to back data reads and writes may occur with no wait states inserted for generating the terminal count information.
摘要翻译：提供DMA控制器用于通过I / O总线在源设备和目标设备之间传输数据。 DMA控制电路包括总线接口单元，用于在每个连续的总线周期的开始处提供总线尺寸信息，并且响应于总线尺寸信息提供前视，用于提供总线尺寸控制信号。响应于总线尺寸控制信号的DMA控制电路在连续传送周期期间控制总线宽度。通过动态调整DMA控制电路，背靠背数据读取和写入可能会在没有插入等待状态以产生终端计数信息的情况下进行。

9. 再颁专利

USRE43235E1 Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator 有权
标题翻译：单块虚拟帧缓冲区转换为多块物理块，用于多块显示刷新生成器
公开(公告)号：USRE43235E1
公开(公告)日：2012-03-13
申请号：US12789856
申请日：2010-05-28
申请人： Takatoshi Ishii , Edmund Cheung , Sherwood Brannon
发明人： Takatoshi Ishii , Edmund Cheung , Sherwood Brannon
IPC分类号： G06F12/10 , G06F12/06 , G09G3/37 , G09G5/00 , G09G5/36
CPC分类号： G09G5/39 , G09G5/14 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2330/021
摘要： A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.
摘要翻译：与电池供电设备一起使用的片上系统（SOC）图形控制器允许降低功耗的显示模式。微处理器写入作为虚拟存储器中单个连续地址块的帧缓冲器。存储器管理单元（MMU）将帧缓冲器地址转换为多个物理块。图形控制器从多个物理块中获取像素，包括片上存储器中的块和外部存储器中的块。在低功耗模式下，像素只能从较低功耗的片上存储器中取出，而不是较高功率的外部存储器。定义一个较小的显示窗口，窗口外的像素将被虚拟数据替代，从而消除外部存储器提取。较小的显示窗口落在片内存储器的第一个块内。在待机模式下，状态和其他信息可以显示在较小的显示窗口中，全屏显示全功能模式。

10. 发明授权

US5477242A Display adapter for virtual VGA support in XGA native mode 失效
标题翻译：显示适配器，用于XGA纯模式下的虚拟VGA支持
公开(公告)号：US5477242A
公开(公告)日：1995-12-19
申请号：US177105
申请日：1994-01-03
申请人： Stephen P. Thompson , Darwin P. Rackley , Sherwood Brannon
发明人： Stephen P. Thompson , Darwin P. Rackley , Sherwood Brannon
IPC分类号： G09G5/393 , G09G5/00 , G09G5/36 , G09G5/39 , G09G5/395
CPC分类号： G09G5/363
摘要： Method and apparatus for enabling an XGA display adapter selectively to support VGA graphics mode virtualization during native mode operation of the adapter by rendering VGA graphics assist hardware and certain VGA registers accessible. In a preferred embodiment, the invention comprises an XGA display adapter which includes a host interface for interfacing the display adapter with a central processing unit (CPU) of a personal computer (PC), VGA graphics assist hardware for performing VGA graphics assist functions, a memory controller for reading and writing a video memory of the PC as requested by the CPU during video memory accesses, and a display interface for generating control and timing signals to a display of the PC. The XGA display adapter also includes a XGA Operating Mode Register having three control bits which can be written by applications software selectively to enable or disable the virtual VGA function of the present invention. When the virtual VGA function is enabled, logic circuitry within the host interface examines the CPU address associated with each video memory access to determine whether the access comprises a virtual VGA memory access, rather than a native memory access. If so, the host interface routes CPU address and any data to be written to the video memory at that address, which performs the appropriate graphics assist operations on the address and/or data to enable the requested operation accurately to be performed on a virtual VGA memory buffer portion of the video memory by the memory controller.
摘要翻译：用于使XGA显示适配器通过渲染VGA图形辅助硬件和某些VGA寄存器可访问的本地模式操作期间，有选择地支持VGA图形模式虚拟化的方法和装置。在优选实施例中，本发明包括一个XGA显示适配器，其包括用于将显示适配器与个人计算机（PC）的中央处理单元（CPU）接口的主机接口，用于执行VGA图形辅助功能的VGA图形辅助硬件，存储器控制器，用于在视频存储器访问期间根据CPU请求读取和写入PC的视频存储器;以及显示接口，用于向PC的显示器生成控制和定时信号。 XGA显示适配器还包括具有三个控制位的XGA操作模式寄存器，其可以由应用软件选择性地写入以启用或禁用本发明的虚拟VGA功能。当启用虚拟VGA功能时，主机接口内的逻辑电路检查与每个视频存储器访问相关联的CPU地址，以确定访问是否包含虚拟VGA存储器访问，而不是本地存储器访问。如果是这样，主机接口将CPU地址和要写入到该地址的视频存储器的任何数据进行路由，该地址和/或数据对地址和/或数据执行适当的图形辅助操作，以使所请求的操作准确地在虚拟VGA 存储器控制器的视频存储器的存储器缓冲部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式