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1. 发明授权

US5673414A Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device 失效
标题翻译：侦听I / O总线，并使处理器缓存无效，从而在另一个I / O设备中的一个I / O设备和可高速缓存的存储器之间进行存储器数据传输
公开(公告)号：US5673414A
公开(公告)日：1997-09-30
申请号：US327136
申请日：1994-10-21
申请人： Nader Amini , Bechara Fouad Boury , Sherwood Brannon , Richard Louis Horne
发明人： Nader Amini , Bechara Fouad Boury , Sherwood Brannon , Richard Louis Horne
IPC分类号： G06F12/08 , G06F13/00 , G06F13/36 , G06F13/40
CPC分类号： G06F12/0835
摘要： In a computer system that contains an input output (I/O) bus connecting to I/O devices, a central processing unit (CPU), a CPU cache memory, a system memory not directly accessible via the I/O bus, and a system bus used for conducting data transfers between the I/O bus and both the CPU cache and system memory, a method and apparatus are provided to allow addressable memory locations in both the system memory and I/O devices coupled to the I/O bus to be cacheable in the CPU cache. The I/O bus supports data transfers between pairs of I/O devices, as well as data transfers between individual I/O devices and the system which presents a problem of maintaining coherency in the CPU cache when data is written by one I/O device to a cacheable memory location in another I/O device. The present solution employs a snoop/data invalidation function at the system interface to the I/O bus to determine when a memory location in an I/O device coupled to the I/O bus is being written to by another I/O device coupled to the I/O bus. If such a write is taking place, it is then determined if the address of the location being written is in an address range predesignated as cacheable; if so, then the CPU cache controller or other device controlling the CPU cache is notified that memory at a cacheable location in an I/O device has been overwritten.
摘要翻译：在包含连接到I / O设备的输入输出（I / O）总线的计算机系统中，中央处理单元（CPU），CPU高速缓冲存储器，不能通过I / O总线直接访问的系统存储器和用于在I / O总线与CPU高速缓存和系统存储器之间进行数据传输的系统总线，提供了一种方法和装置，以允许耦合到I / O总线的系统存储器和I / O设备中的可寻址存储器位置可缓存在CPU缓存中。 I / O总线支持I / O设备之间的数据传输，以及单个I / O设备与系统之间的数据传输，当数据由一个I / O写入时，会出现维护CPU高速缓存中的一致性问题设备到另一个I / O设备中的可缓存存储器位置。本解决方案在I / O总线的系统接口处采用窥探/数据无效功能，以确定耦合到I / O总线的I / O设备中的存储器位置何时被另一个耦合的I / O设备写入到I / O总线。如果发生这样的写入，则确定正在写入的位置的地址是否在预先指定为可缓存的地址范围内; 如果是这样，则CPU缓存控制器或控制CPU高速缓存的其他设备被通知，I / O设备中可缓存位置的存储器已被覆盖。

2. 发明授权

US5966728A Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device 失效
标题翻译：用于窥探数据写入到扩展存储器设备中的可缓存存储器位置的计算机系统和方法
公开(公告)号：US5966728A
公开(公告)日：1999-10-12
申请号：US490648
申请日：1995-06-15
申请人： Nader Amini , Bechara Fouad Boury , Sherwood Brannon , Richard Louis Horne
发明人： Nader Amini , Bechara Fouad Boury , Sherwood Brannon , Richard Louis Horne
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0835
摘要： A computer system and method allow memory locations in both system memory and expansion memory devices coupled to an input/output (I/O) bus to be cacheable in a central processing unit (CPU) cache. The computer system contains an I/O bus connected to I/O devices and an expansion bus connected to expansion memory devices, a system memory not accessible via the I/O bus or expansion bus, and the system bus used for conducting data transfers between the I/O bus and both the CPU cache and system memory. The I/O bus supports data transfers between pairs of I/O devices, and I/O devices and expansion memory devices on the expansion bus, as well as data transfers between individual I/O devices and the system, which presents a problem of maintaining coherency in the CPU cache when data is written by one I/O device or expansion memory device to a cacheable memory location in another I/O device or expansion memory device. The computer system employs a snoop/data invalidation function at the system interface to the I/O bus to determine when a memory location in an expansion memory device coupled to the expansion bus is being written to by another expansion memory device coupled to the expansion bus or an I/O device coupled to the I/O bus. If such a write is taking place, it is then determined if the address of the location being written is in and address range predesignated as cacheable; if so, then the CPU cache controller or other device controlling the CPU cache is notified that memory at a cacheable location in an expansion memory device has been overwritten.
摘要翻译：计算机系统和方法允许耦合到输入/输出（I / O）总线的系统存储器和扩展存储器设备中的存储器位置在中央处理单元（CPU）高速缓存中可高速缓存。计算机系统包含连接到I / O设备的I / O总线和连接到扩展存储器设备的扩展总线，不能通过I / O总线或扩展总线访问的系统存储器，以及用于进行数据传输的系统总线 I / O总线以及CPU缓存和系统内存。 I / O总线支持I / O设备之间的数据传输，扩展总线上的I / O设备和扩展存储设备之间的数据传输，以及各个I / O设备与系统之间的数据传输，当数据由一个I / O设备或扩展存储器设备写入到另一个I / O设备或扩展存储器设备中的可高速缓存存储器位置时，保持CPU高速缓存中的一致性。计算机系统在I / O总线的系统接口处采用窥探/数据无效功能，以确定耦合到扩展总线的扩展存储器件中的存储器位置何时被耦合到扩展总线的另一个扩展存储器件写入或耦合到I / O总线的I / O设备。如果发生这样的写入，则确定正在写入的位置的地址是否在预先指定为可缓存的地址范围内; 如果是这样，则CPU缓存控制器或控制CPU高速缓存的其他设备被通知，扩展存储器设备中的可缓存位置处的存储器已被覆盖。

3. 发明授权

US5644729A Bidirectional data buffer for a bus-to-bus interface unit in a computer system 失效
标题翻译：计算机系统中总线到总线接口单元的双向数据缓冲器
公开(公告)号：US5644729A
公开(公告)日：1997-07-01
申请号：US282159
申请日：1994-07-28
申请人： Nader Amini , Bechara Fouad Boury , Sherwood Brannon , Richard Louis Horne , Terence Joseph Lohman
发明人： Nader Amini , Bechara Fouad Boury , Sherwood Brannon , Richard Louis Horne , Terence Joseph Lohman
IPC分类号： G06F13/28 , G06F13/16 , G06F13/40 , G06F13/00
CPC分类号： G06F13/1673 , G06F13/4059
摘要： A method and system are provided for controlling data transfer between a system memory connected to a system bus and at least one input/output (I/O) device connected to an I/O bus in a computer system. The system bus is coupled to the I/O bus by a bus interface unit comprising a first pair of buffers connected in series between the I/O bus and the system bus, and a second pair of buffers connected in series between the I/O bus and the system bus and in parallel with the first pair of buffers. Each of the buffers in each of the pairs is used for bidirectional data transfer between the system bus and the I/O bus.
摘要翻译：提供了一种用于控制连接到系统总线的系统存储器与连接到计算机系统中的I / O总线的至少一个输入/输出（I / O）设备之间的数据传输的方法和系统。系统总线通过总线接口单元耦合到I / O总线，总线接口单元包括串联连接在I / O总线和系统总线之间的第一对缓冲器，以及串联连接在I / O之间的第二对缓冲器总线和系统总线，并与第一对缓冲器并联。每对中的每个缓冲区用于系统总线和I / O总线之间的双向数据传输。

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