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1. 发明授权

US07538593B2 Circuit and method to convert a single ended signal to duplicated signals 有权
标题翻译：将单端信号转换为重复信号的电路和方法
公开(公告)号：US07538593B2
公开(公告)日：2009-05-26
申请号：US11710270
申请日：2007-02-23
申请人： Prabhat Agarwal , Mayank Goel , Pradip Mandal
发明人： Prabhat Agarwal , Mayank Goel , Pradip Mandal
IPC分类号： G06F1/04
CPC分类号： H03K5/151
摘要： A circuit to convert a single ended signal to differential signals is disclosed. The circuit has two paths with each of the two paths comprising a plurality of stages. The number of stages in each of the two paths is the same. A first path of the two paths includes a buffer stage and at least one inverter stage. A second path of the two paths includes at least two inverter stages. The buffer stage has a delay matched to that of a first inverter stage of the second path. The buffer stage comprises a first pair of transistors comprising a first transistor of a first category operatively connected to a first transistor of a second category with their channel connections being connected in series.
摘要翻译：公开了将单端信号转换为差分信号的电路。该电路具有两条路径，其中两条路径中的每条路径包括多个级。两个路径中的每个路段的数量是相同的。两个路径的第一路径包括缓冲段和至少一个逆变器级。两路径的第二路径包括至少两个逆变器级。缓冲级具有与第二路径的第一反相器级的延迟匹配的延迟。缓冲级包括第一对晶体管，其包括第一类别的第一晶体管，其可操作地连接到第二类别的第一晶体管，其沟道连接串联连接。

2. 发明申请

US20080204096A1 Circuit and method to convert a single ended signal to duplicated signals 有权
标题翻译：将单端信号转换为重复信号的电路和方法
公开(公告)号：US20080204096A1
公开(公告)日：2008-08-28
申请号：US11710270
申请日：2007-02-23
申请人： Prabhat Agarwal , Mayank Goel , Pradip Mandal
发明人： Prabhat Agarwal , Mayank Goel , Pradip Mandal
IPC分类号： H03K5/151
CPC分类号： H03K5/151
摘要： A circuit to convert a single ended signal to differential signals is disclosed. The circuit has two paths with each of the two paths comprising a plurality of stages. The number of stages in each of the two paths is the same. A first path of the two paths includes a buffer stage and at least one inverter stage. A second path of the two paths includes at least two inverter stages. The buffer stage has a delay matched to that of a first inverter stage of the second path. The buffer stage comprises a first pair of transistors comprising a first transistor of a first category operatively connected to a first transistor of a second category with their channel connections being connected in series.
摘要翻译：公开了将单端信号转换为差分信号的电路。该电路具有两条路径，其中两条路径中的每条路径包括多个级。两个路径中的每个路段的数量是相同的。两个路径的第一路径包括缓冲段和至少一个逆变器级。两路径的第二路径包括至少两个逆变器级。缓冲级具有与第二路径的第一反相器级的延迟匹配的延迟。缓冲级包括第一对晶体管，其包括第一类别的第一晶体管，其可操作地连接到第二类别的第一晶体管，其沟道连接串联连接。

3. 发明申请

US20070279091A1 Digital Voltage Level Shifter 审中-公开
标题翻译：数字电压电平变换器
公开(公告)号：US20070279091A1
公开(公告)日：2007-12-06
申请号：US11663406
申请日：2004-09-22
申请人： Mayank Goel , Prabhat Agarwal
发明人： Mayank Goel , Prabhat Agarwal
IPC分类号： H03K3/356
CPC分类号： H03K3/356147 , H03K17/102
摘要： A digital voltage level shifter for converting an input signal with a low voltage swing to an output signal with a high voltage swing comprises a first inverter stage for generating an inverted signal from an input signal, the inverted signal having a voltage swing between a core voltage and ground, and a second inverter stage for producing an anti-phase signal from the inverted input signal, the anti-phase signal having a voltage swing between the core voltage and ground. The first and second inverters each drive a respective thin gate NMOS transistor connected in cascode with a respective NMOS transistor. The sources of the first and second thin gate NMOS transistors are connected to ground. The gates of the NMOS transistors are connected to the output of the respective inverters through a respective capacitor and are referenced to the core voltage through a respective resistor. The drains of the NMOS transistors are connected to an output circuit to provide an output signal having a voltage higher than the core voltage.
摘要翻译：用于将具有低电压摆幅的输入信号转换为具有高电压摆幅的输出信号的数字电压电平移位器包括用于从输入信号产生反相信号的第一反相器级，反相信号具有在核心电压以及用于从反相输入信号产生反相信号的第二反相器级，反相信号在核心电压和地之间具有电压摆幅。第一和第二反相器各自驱动以共源共栅连接的相应的薄栅极NMOS晶体管与相应的NMOS晶体管。第一和第二薄栅NMOS晶体管的源极连接到地。 NMOS晶体管的栅极通过相应的电容器连接到各个反相器的输出，并且通过相应的电阻器参考核心电压。 NMOS晶体管的漏极连接到输出电路，以提供具有高于核心电压的电压的输出信号。

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