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1. 发明申请

US20080122116A1 METHOD OF FORMING METAL LAYER WIRING STRUCTURE ON BACKSIDE OF WAFER, METAL LAYER WIRING STRUCTURE FORMED USING THE METHOD, METHOD OF STACKING CHIP PACKAGE, AND CHIP PACKAGE STACK STRUCTURE FORMED USING THE METHOD 审中-公开
标题翻译：使用该方法形成的金属层布线结构的方法，使用该方法形成的金属层布线结构，堆叠芯片封装的方法和使用该方法形成的芯片封装堆叠结构
公开(公告)号：US20080122116A1
公开(公告)日：2008-05-29
申请号：US11942529
申请日：2007-11-19
申请人： Myeong-Soon PARK , In-Young LEE , Ho-Jin LEE , Yong-Tae OH
发明人： Myeong-Soon PARK , In-Young LEE , Ho-Jin LEE , Yong-Tae OH
IPC分类号： H01L21/58 , H01L23/522
CPC分类号： H01L25/0657 , H01L23/296 , H01L23/481 , H01L24/12 , H01L24/16 , H01L24/90 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/16147 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2224/90 , H01L2225/06517 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01059 , H01L2924/01078 , H01L2924/01079
摘要： Provided are a method of forming a metal layer wiring structure on the backside of a wafer, a metal layer wiring structure formed using the method, a method of stacking a chip package, and a chip package stack structure formed using the method. The method of stacking a chip package includes: forming recess patterns on a backside of wafers; forming a passivation layer on the backside of the wafers except for an area corresponding to a through electrode; forming a metal layer on the passivation layer; planarizing the metal layers to expose only the recess patterns; forming a lower insulating layer on the planarized metal layers except for an area corresponding to a contact portion with another wafer; forming an adhesive layer on the lower insulating layer of each of the wafers; and adhering the wafers to one another, wherein the recess patterns are formed using a laser.
摘要翻译：提供了在晶片的背面形成金属层布线结构的方法，使用该方法形成的金属层布线结构，堆叠芯片封装的方法以及使用该方法形成的芯片封装堆叠结构。堆叠芯片封装的方法包括：在晶片的背面形成凹陷图案; 在除了对应于通孔的区域之外的晶片的背面上形成钝化层; 在钝化层上形成金属层; 平坦化金属层以仅露出凹部图案; 在除了与另一晶片的接触部分相对应的区域之外的平坦化金属层上形成下绝缘层; 在每个晶片的下绝缘层上形成粘合剂层; 并且将晶片彼此粘合，其中使用激光形成凹部图案。

2. 发明申请

US20080128905A1 WAFER LEVEL CHIP SCALE PACKAGE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR CHIP MODULE INCLUDING THE WAFER LEVEL CHIP SCALE PACKAGE 有权
标题翻译： WAFER LEVEL CHIP SCALE包装及其制造方法，以及半导体芯片模块，包括WAFER LEVEL CHIP SCALE包装
公开(公告)号：US20080128905A1
公开(公告)日：2008-06-05
申请号：US11950251
申请日：2007-12-04
申请人： In-Young LEE , Dong-Ho LEE , Nam-Seog KIM , Hyun-Soo CHUNG , Ho-Jin LEE , Myeong-Soo PARK
发明人： In-Young LEE , Dong-Ho LEE , Nam-Seog KIM , Hyun-Soo CHUNG , Ho-Jin LEE , Myeong-Soo PARK
IPC分类号： H01L23/488 , H01L21/44
CPC分类号： H01L23/525 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L24/16 , H01L2224/05001 , H01L2224/05008 , H01L2224/05026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05548 , H01L2224/05569 , H01L2224/056 , H01L2224/05647 , H01L2224/05666 , H01L2224/11334 , H01L2224/1147 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.
摘要翻译：提供了其中在晶片级应用再分配处理的晶片级芯片级封装，其制造方法以及包括晶片级芯片级封装的半导体芯片模块。晶片级芯片级封装包括具有接合焊盘的半导体芯片，设置在半导体芯片上以暴露焊盘的第一绝缘层，设置在暴露的焊盘和第一绝缘层上的再分配线，牺牲层设置在所述再分配线的再分配衬垫的下方，设置在所述再分配线上的第二绝缘层，以暴露所述再分配衬垫并且包括设置在所述牺牲层旁边的裂纹诱导孔，以及附接到所述再分布衬垫的外部连接端子。

3. 发明申请

US20080230923A1 CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE CHIP STACK PACKAGE 审中-公开
标题翻译：芯片堆叠包装和制造芯片堆叠包装的方法
公开(公告)号：US20080230923A1
公开(公告)日：2008-09-25
申请号：US12051619
申请日：2008-03-19
申请人： Cha-Jea JO , Myung-Kee CHUNG , Nam-Seog KIM , In-Young LEE , Seok-Ho KIM , Ho-Jin LEE , Ju-Il CHOI , Chang-Woo SHIN
发明人： Cha-Jea JO , Myung-Kee CHUNG , Nam-Seog KIM , In-Young LEE , Seok-Ho KIM , Ho-Jin LEE , Ju-Il CHOI , Chang-Woo SHIN
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L23/3128 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05025 , H01L2224/05124 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/15311 , H01L2224/05599
摘要： A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.
摘要翻译：芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。基板具有形成在布线图案上的布线图案和种子层。每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。粘合层介于基片和芯片之一之间以及芯片之间。每个粘合层具有连接到第一通孔的第二通孔。插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

4. 发明申请

US20090085224A1 STACK-TYPE SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：堆叠型半导体封装
公开(公告)号：US20090085224A1
公开(公告)日：2009-04-02
申请号：US12244591
申请日：2008-10-02
申请人： Ju-Il CHOI , Hyun-Soo CHUNG , In-Young LEE , Ho-Jin LEE , Son-Kwan HWANG
发明人： Ju-Il CHOI , Hyun-Soo CHUNG , In-Young LEE , Ho-Jin LEE , Son-Kwan HWANG
IPC分类号： H01L23/538 , H01L21/58
CPC分类号： H01L24/29 , H01L21/561 , H01L23/3121 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/24145 , H01L2224/29101 , H01L2224/9202 , H01L2224/97 , H01L2225/06541 , H01L2225/06551 , H01L2225/06575 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/014 , H01L2224/82 , H01L2924/00
摘要： Provided is a stack-type semiconductor package including a base chip having a circuit formed on one of its surfaces, at least one stack chip having a circuit stacked on the base chip, an adhesive interposed between the base chip and the stack chip, and signal transmission members formed along a lateral surface of the stack chip. The fabrication process of this stack-type semiconductor package may be simplified and the number of process operations may be lessened, thereby reducing the production time and cost. Also, a state of electrical contact of a terminal with a signal transmission member may be solidified, thereby improving the reliability of the stack-type semiconductor package. Furthermore, new post-type signal transmission members are adopted instead of wires or electrodes so that the structural stability and productivity of the stack-type semiconductor package may be markedly enhanced.
摘要翻译：提供了一种堆叠型半导体封装，其包括具有形成在其一个表面上的电路的基底芯片，具有堆叠在基底芯片上的电路的至少一个堆叠芯片，插入在基底芯片和堆叠芯片之间的粘合剂，以及信号传输构件沿着堆叠芯片的侧表面形成。可以简化该堆叠型半导体封装的制造工艺，并且可以减少工艺操作的数量，从而减少生产时间和成本。此外，端子与信号传输部件的电接触的状态可以被固化，从而提高堆叠型半导体封装的可靠性。此外，采用新的后置型信号传输构件代替线或电极，从而可以显着提高堆叠型半导体封装的结构稳定性和生产率。

5. 发明申请

US20090008790A1 SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有电极的半导体器件及其制造方法
公开(公告)号：US20090008790A1
公开(公告)日：2009-01-08
申请号：US12132925
申请日：2008-06-04
申请人： Ho-Jin LEE , Nam-Seog KIM , Yong-Chai KWON , Hyun-Soo CHUNG , In-Young LEE , Son-Kwan HWANG
发明人： Ho-Jin LEE , Nam-Seog KIM , Yong-Chai KWON , Hyun-Soo CHUNG , In-Young LEE , Son-Kwan HWANG
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/481 , H01L24/03 , H01L24/06 , H01L24/13 , H01L24/32 , H01L25/0657 , H01L2224/02372 , H01L2224/034 , H01L2224/036 , H01L2224/0401 , H01L2224/05009 , H01L2224/05011 , H01L2224/05552 , H01L2224/05559 , H01L2224/05561 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/06136 , H01L2224/06181 , H01L2224/08146 , H01L2224/32145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/19041 , H01L2924/00014
摘要： A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole.
摘要翻译：公开了一种具有通孔的半导体器件及其制造方法。在一个实施例中，半导体器件包括形成在半导体衬底上的第一绝缘层。具有用于露出第一绝缘层的一部分的第一孔的布线层形成在第一绝缘层上。第二绝缘层形成在布线层的上部和第一孔中。具有第二孔径以暴露第二绝缘层的一部分的导电焊盘形成在第二绝缘层上。通过第一和第二绝缘层和半导体衬底的上部形成宽度比第一和第二孔的宽度窄的通孔。在通孔中形成贯通电极。

6. 发明申请

US20160233155A1 SEMICONDUCTOR DEVICE, FABRICATING METHOD THEREOF AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及其制造方法及其半导体器件包括半导体器件
公开(公告)号：US20160233155A1
公开(公告)日：2016-08-11
申请号：US15130904
申请日：2016-04-15
申请人： Ho-Jin LEE , Tae-Je CHO , Dong-Hyeon JANG , Ho-Geon SONG , Se-Young JEONG , Un-Byoung KANG , Min-Seung YOON
发明人： Ho-Jin LEE , Tae-Je CHO , Dong-Hyeon JANG , Ho-Geon SONG , Se-Young JEONG , Un-Byoung KANG , Min-Seung YOON
IPC分类号： H01L23/498 , H01L23/48
CPC分类号： H01L23/49844 , H01L21/76831 , H01L21/76844 , H01L21/76898 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/525 , H01L25/0657 , H01L2224/02372 , H01L2224/05009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06544 , H01L2924/15311
摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.
摘要翻译：在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。第二表面限定再分布沟槽。基板具有贯穿其中的通孔。半导体器件还包括设置在通孔中的贯通孔。通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。通孔还可以包括邻近阻挡层的导电连接器。半导体器件还包括形成在衬底的第二表面上的绝缘层图案。绝缘层图案限定了暴露通孔的顶表面的区域的开口。半导体器件包括设置在沟槽中并与通孔电连接的再分配层。绝缘层图案与导电连接器的区域重叠。

7. 发明申请

US20120292782A1 MICROELECTRONIC DEVICES HAVING CONDUCTIVE THROUGH VIA ELECTRODES INSULATED BY GAP REGIONS 有权
标题翻译：具有通过GAP区域绝缘的电极导电的微电子器件
公开(公告)号：US20120292782A1
公开(公告)日：2012-11-22
申请号：US13474992
申请日：2012-05-18
申请人： Ho-Jin LEE , Byung Lyul Park , SeYoung Jeong , Hyunsoo Chung , Gilheyun Choi
发明人： Ho-Jin LEE , Byung Lyul Park , SeYoung Jeong , Hyunsoo Chung , Gilheyun Choi
IPC分类号： H01L23/498
CPC分类号： H01L21/76898 , H01L21/7682 , H01L23/481 , H01L2224/02372 , H01L2224/0401 , H01L2224/05 , H01L2224/05548 , H01L2224/06181 , H01L2224/13 , H01L2224/13023 , H01L2224/13024 , H01L2224/13025
摘要： A microelectronic device includes a substrate having a trench extending therethrough between an active surface thereof and an inactive surface thereof opposite the active surface, a conductive via electrode extending through the substrate between sidewalls of the trench, and an insulating layer extending along the inactive surface of the substrate outside the trench and extending at least partially into the trench. The insulating layer defines a gap region in the trench that separates the substrate and the via electrode. Related devices and methods of fabrication are also discussed.
摘要翻译：微电子器件包括：衬底，其具有在其活性表面与其与有源表面相对的非活性表面之间延伸穿过的沟槽;在沟槽的侧壁之间延伸通过衬底的导电通孔电极，以及沿沟槽的非活性表面延伸的绝缘层衬底在沟槽外部并且至少部分地延伸到沟槽中。绝缘层限定沟槽中的间隙区域，其分离衬底和通孔电极。还讨论了相关装置和制造方法。

8. 发明申请

US20120074584A1 MULTI-LAYER TSV INSULATION AND METHODS OF FABRICATING THE SAME 有权
标题翻译：多层TSV绝缘及其制造方法
公开(公告)号：US20120074584A1
公开(公告)日：2012-03-29
申请号：US13049661
申请日：2011-03-16
申请人： Ho-Jin LEE , SeYoung Jeong , Jae-hyun Phee , Jung-Hwan Kim , Tae Hong Min
发明人： Ho-Jin LEE , SeYoung Jeong , Jae-hyun Phee , Jung-Hwan Kim , Tae Hong Min
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/76831 , H01L23/481 , H01L25/105 , H01L2224/0557 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/12044 , H01L2924/15311 , H01L2924/00014
摘要： Provided is a semiconductor device. The semiconductor device may include a substrate and a stacked insulation layer on a sidewall of an opening which penetrates the substrate. The stacked insulation layer can include at least one first insulation layer and at least one second insulation layer whose dielectric constant is different than that of the first insulation layer. One insulation layer may be a polymer and one insulation layer may be a silicon based insulation layer. The insulation layers may be uniform in thickness or may vary as a distance from the substrate changes.
摘要翻译：提供一种半导体器件。半导体器件可以包括衬底和在穿透衬底的开口的侧壁上的层叠绝缘层。层叠绝缘层可以包括至少一个第一绝缘层和至少一个第二绝缘层，其介电常数不同于第一绝缘层的介电常数。一个绝缘层可以是聚合物，一个绝缘层可以是硅基绝缘层。绝缘层的厚度可以是均匀的，或者可以随着离开衬底的距离而改变。

9. 发明申请

US20110115340A1 TOUCH PANEL DEVICE 有权
标题翻译：触摸板设备
公开(公告)号：US20110115340A1
公开(公告)日：2011-05-19
申请号：US12948211
申请日：2010-11-17
申请人： Ho-Jin LEE
发明人： Ho-Jin LEE
IPC分类号： H01L41/053
CPC分类号： G06F3/041 , G06F3/016
摘要： A touch panel device in which a support portion is provided to include an actuator for generating vibration giving an excellent sense of touch without the need for a separate mounting space. To this end, the touch panel device having a front cover portion, a touch sensor unit divided into an upper transparent electrode layer and a lower transparent electrode layer, and a substrate provided under the touch sensor portion includes an actuator for delivering vibration to the front cover portion, a reinforcing portion having the actuator attached thereto to attach the actuator to the touch sensor unit, and a support portion formed on the substrate to provide an opening in a first side thereof and a closed second side, such that the actuator is inserted into and coupled to the opening and the support portion supports the actuator to deliver the vibration of the actuator to the front cover portion.
摘要翻译：一种触摸面板装置，其中提供支撑部分以包括用于产生振动的致动器，从而具有优异的触摸感，而不需要单独的安装空间。为此，具有前盖部分，分为上透明电极层和下透明电极层的触摸传感器单元和设置在触摸传感器部分下方的基板的触摸面板装置包括用于将振动传递到前面的致动器覆盖部分，具有附接到其上的致动器以将致动器附接到触摸传感器单元的加强部分，以及形成在基板上的支撑部分，以在其第一侧和闭合的第二侧提供开口，使得致动器被插入并且支撑部分支撑致动器以将致动器的振动传递到前盖部分。

10. 发明申请

US20150279825A1 SEMICONDUCTOR DEVICES HAVING HYBRID STACKING STRUCTURES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有混合堆叠结构的半导体器件及其制造方法
公开(公告)号：US20150279825A1
公开(公告)日：2015-10-01
申请号：US14669291
申请日：2015-03-26
申请人： Pil-Kyu KANG , Byung Lyul PARK , Taeyeong KIM , Yeun-Sang PARK , Dosun LEE , Ho-Jin LEE , Jinho CHUN , Ju-il CHOI , Yi Koan HONG
发明人： Pil-Kyu KANG , Byung Lyul PARK , Taeyeong KIM , Yeun-Sang PARK , Dosun LEE , Ho-Jin LEE , Jinho CHUN , Ju-il CHOI , Yi Koan HONG
IPC分类号： H01L25/16 , H01L23/538 , H01L23/495 , H01L21/48 , H01L21/768 , H01L21/66 , H01L25/00 , H01L21/304
CPC分类号： H01L25/50 , H01L21/304 , H01L21/561 , H01L21/76898 , H01L22/32 , H01L23/3128 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05568 , H01L2224/0557 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/08146 , H01L2224/131 , H01L2224/13124 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/81191 , H01L2224/81193 , H01L2224/9202 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2225/06596 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/81 , H01L2224/11 , H01L2224/03 , H01L2924/00014 , H01L2924/014
摘要： A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.
摘要翻译：提供具有芯片堆叠和互连端子的半导体器件。芯片堆叠包括彼此堆叠的第一半导体芯片，第二半导体芯片和第三半导体芯片。互连端子电耦合到芯片堆叠。第一半导体芯片包括第一正面和第一背面。第二半导体芯片包括电耦合到第二电路层并穿透第二半导体芯片的第二前表面，第二背面，第二电路层和贯通电极。第三半导体芯片包括第三前表面，与第三前表面相对的第三背面和与第三前表面相邻的第三电路层。第一前表面和第二前表面彼此面对。第三前表面和第二后侧表面彼此面对。

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