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1. 发明申请

US20090085224A1 STACK-TYPE SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：堆叠型半导体封装
公开(公告)号：US20090085224A1
公开(公告)日：2009-04-02
申请号：US12244591
申请日：2008-10-02
申请人： Ju-Il CHOI , Hyun-Soo CHUNG , In-Young LEE , Ho-Jin LEE , Son-Kwan HWANG
发明人： Ju-Il CHOI , Hyun-Soo CHUNG , In-Young LEE , Ho-Jin LEE , Son-Kwan HWANG
IPC分类号： H01L23/538 , H01L21/58
CPC分类号： H01L24/29 , H01L21/561 , H01L23/3121 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/24145 , H01L2224/29101 , H01L2224/9202 , H01L2224/97 , H01L2225/06541 , H01L2225/06551 , H01L2225/06575 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/014 , H01L2224/82 , H01L2924/00
摘要： Provided is a stack-type semiconductor package including a base chip having a circuit formed on one of its surfaces, at least one stack chip having a circuit stacked on the base chip, an adhesive interposed between the base chip and the stack chip, and signal transmission members formed along a lateral surface of the stack chip. The fabrication process of this stack-type semiconductor package may be simplified and the number of process operations may be lessened, thereby reducing the production time and cost. Also, a state of electrical contact of a terminal with a signal transmission member may be solidified, thereby improving the reliability of the stack-type semiconductor package. Furthermore, new post-type signal transmission members are adopted instead of wires or electrodes so that the structural stability and productivity of the stack-type semiconductor package may be markedly enhanced.
摘要翻译：提供了一种堆叠型半导体封装，其包括具有形成在其一个表面上的电路的基底芯片，具有堆叠在基底芯片上的电路的至少一个堆叠芯片，插入在基底芯片和堆叠芯片之间的粘合剂，以及信号传输构件沿着堆叠芯片的侧表面形成。可以简化该堆叠型半导体封装的制造工艺，并且可以减少工艺操作的数量，从而减少生产时间和成本。此外，端子与信号传输部件的电接触的状态可以被固化，从而提高堆叠型半导体封装的可靠性。此外，采用新的后置型信号传输构件代替线或电极，从而可以显着提高堆叠型半导体封装的结构稳定性和生产率。

2. 发明申请

US20090008790A1 SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有电极的半导体器件及其制造方法
公开(公告)号：US20090008790A1
公开(公告)日：2009-01-08
申请号：US12132925
申请日：2008-06-04
申请人： Ho-Jin LEE , Nam-Seog KIM , Yong-Chai KWON , Hyun-Soo CHUNG , In-Young LEE , Son-Kwan HWANG
发明人： Ho-Jin LEE , Nam-Seog KIM , Yong-Chai KWON , Hyun-Soo CHUNG , In-Young LEE , Son-Kwan HWANG
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/481 , H01L24/03 , H01L24/06 , H01L24/13 , H01L24/32 , H01L25/0657 , H01L2224/02372 , H01L2224/034 , H01L2224/036 , H01L2224/0401 , H01L2224/05009 , H01L2224/05011 , H01L2224/05552 , H01L2224/05559 , H01L2224/05561 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/06136 , H01L2224/06181 , H01L2224/08146 , H01L2224/32145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/19041 , H01L2924/00014
摘要： A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole.
摘要翻译：公开了一种具有通孔的半导体器件及其制造方法。在一个实施例中，半导体器件包括形成在半导体衬底上的第一绝缘层。具有用于露出第一绝缘层的一部分的第一孔的布线层形成在第一绝缘层上。第二绝缘层形成在布线层的上部和第一孔中。具有第二孔径以暴露第二绝缘层的一部分的导电焊盘形成在第二绝缘层上。通过第一和第二绝缘层和半导体衬底的上部形成宽度比第一和第二孔的宽度窄的通孔。在通孔中形成贯通电极。

3. 发明申请

US20090267211A1 WAFER LEVEL PACKAGE AND METHOD OF FABRICATING THE SAME 有权
标题翻译： WAFER LEVEL PACKAGE及其制作方法
公开(公告)号：US20090267211A1
公开(公告)日：2009-10-29
申请号：US12498913
申请日：2009-07-07
申请人： Hyun-Soo CHUNG , In-Young LEE , Son-Kwan HWANG , Dong-Ho LEE , Seong-Deok HWANG
发明人： Hyun-Soo CHUNG , In-Young LEE , Son-Kwan HWANG , Dong-Ho LEE , Seong-Deok HWANG
IPC分类号： H01L23/52 , H01L23/538 , H01L23/48
CPC分类号： H01L25/50 , H01L21/76898 , H01L25/0657 , H01L29/0657 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/0557 , H01L2224/06181 , H01L2224/13025 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2225/06586 , H01L2924/0002 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01093 , H01L2224/11 , H01L2224/05552
摘要： Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.
摘要翻译：提供了晶片级封装及其制造方法。在一个实施例中，方法之一包括形成在晶片上具有连接焊盘的半导体芯片，图案化晶片的底表面以在连接焊盘下方形成沟槽，图案化沟槽的底表面以形成通孔，并且通过通孔形成连接到连接垫的连接装置。本发明提供了与传统封装相比，具有减小的厚度，较低的制造成本和增加的可靠性的晶片级封装。

4. 发明申请

US20080230923A1 CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE CHIP STACK PACKAGE 审中-公开
标题翻译：芯片堆叠包装和制造芯片堆叠包装的方法
公开(公告)号：US20080230923A1
公开(公告)日：2008-09-25
申请号：US12051619
申请日：2008-03-19
申请人： Cha-Jea JO , Myung-Kee CHUNG , Nam-Seog KIM , In-Young LEE , Seok-Ho KIM , Ho-Jin LEE , Ju-Il CHOI , Chang-Woo SHIN
发明人： Cha-Jea JO , Myung-Kee CHUNG , Nam-Seog KIM , In-Young LEE , Seok-Ho KIM , Ho-Jin LEE , Ju-Il CHOI , Chang-Woo SHIN
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L23/3128 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05025 , H01L2224/05124 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/15311 , H01L2224/05599
摘要： A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.
摘要翻译：芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。基板具有形成在布线图案上的布线图案和种子层。每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。粘合层介于基片和芯片之一之间以及芯片之间。每个粘合层具有连接到第一通孔的第二通孔。插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

5. 发明申请

US20080128905A1 WAFER LEVEL CHIP SCALE PACKAGE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR CHIP MODULE INCLUDING THE WAFER LEVEL CHIP SCALE PACKAGE 有权
标题翻译： WAFER LEVEL CHIP SCALE包装及其制造方法，以及半导体芯片模块，包括WAFER LEVEL CHIP SCALE包装
公开(公告)号：US20080128905A1
公开(公告)日：2008-06-05
申请号：US11950251
申请日：2007-12-04
申请人： In-Young LEE , Dong-Ho LEE , Nam-Seog KIM , Hyun-Soo CHUNG , Ho-Jin LEE , Myeong-Soo PARK
发明人： In-Young LEE , Dong-Ho LEE , Nam-Seog KIM , Hyun-Soo CHUNG , Ho-Jin LEE , Myeong-Soo PARK
IPC分类号： H01L23/488 , H01L21/44
CPC分类号： H01L23/525 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L24/16 , H01L2224/05001 , H01L2224/05008 , H01L2224/05026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05548 , H01L2224/05569 , H01L2224/056 , H01L2224/05647 , H01L2224/05666 , H01L2224/11334 , H01L2224/1147 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.
摘要翻译：提供了其中在晶片级应用再分配处理的晶片级芯片级封装，其制造方法以及包括晶片级芯片级封装的半导体芯片模块。晶片级芯片级封装包括具有接合焊盘的半导体芯片，设置在半导体芯片上以暴露焊盘的第一绝缘层，设置在暴露的焊盘和第一绝缘层上的再分配线，牺牲层设置在所述再分配线的再分配衬垫的下方，设置在所述再分配线上的第二绝缘层，以暴露所述再分配衬垫并且包括设置在所述牺牲层旁边的裂纹诱导孔，以及附接到所述再分布衬垫的外部连接端子。

6. 发明申请

US20080122116A1 METHOD OF FORMING METAL LAYER WIRING STRUCTURE ON BACKSIDE OF WAFER, METAL LAYER WIRING STRUCTURE FORMED USING THE METHOD, METHOD OF STACKING CHIP PACKAGE, AND CHIP PACKAGE STACK STRUCTURE FORMED USING THE METHOD 审中-公开
标题翻译：使用该方法形成的金属层布线结构的方法，使用该方法形成的金属层布线结构，堆叠芯片封装的方法和使用该方法形成的芯片封装堆叠结构
公开(公告)号：US20080122116A1
公开(公告)日：2008-05-29
申请号：US11942529
申请日：2007-11-19
申请人： Myeong-Soon PARK , In-Young LEE , Ho-Jin LEE , Yong-Tae OH
发明人： Myeong-Soon PARK , In-Young LEE , Ho-Jin LEE , Yong-Tae OH
IPC分类号： H01L21/58 , H01L23/522
CPC分类号： H01L25/0657 , H01L23/296 , H01L23/481 , H01L24/12 , H01L24/16 , H01L24/90 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/16147 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2224/90 , H01L2225/06517 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01059 , H01L2924/01078 , H01L2924/01079
摘要： Provided are a method of forming a metal layer wiring structure on the backside of a wafer, a metal layer wiring structure formed using the method, a method of stacking a chip package, and a chip package stack structure formed using the method. The method of stacking a chip package includes: forming recess patterns on a backside of wafers; forming a passivation layer on the backside of the wafers except for an area corresponding to a through electrode; forming a metal layer on the passivation layer; planarizing the metal layers to expose only the recess patterns; forming a lower insulating layer on the planarized metal layers except for an area corresponding to a contact portion with another wafer; forming an adhesive layer on the lower insulating layer of each of the wafers; and adhering the wafers to one another, wherein the recess patterns are formed using a laser.
摘要翻译：提供了在晶片的背面形成金属层布线结构的方法，使用该方法形成的金属层布线结构，堆叠芯片封装的方法以及使用该方法形成的芯片封装堆叠结构。堆叠芯片封装的方法包括：在晶片的背面形成凹陷图案; 在除了对应于通孔的区域之外的晶片的背面上形成钝化层; 在钝化层上形成金属层; 平坦化金属层以仅露出凹部图案; 在除了与另一晶片的接触部分相对应的区域之外的平坦化金属层上形成下绝缘层; 在每个晶片的下绝缘层上形成粘合剂层; 并且将晶片彼此粘合，其中使用激光形成凹部图案。

7. 发明申请

US20190112693A1 PLASTIC DEFORMATION MAGNESIUM ALLOY HAVING EXCELLENT THERMAL CONDUCTIVITY AND FLAME RETARDANCY, AND PREPARATION METHOD THEREFOR 审中-公开
公开(公告)号：US20190112693A1
公开(公告)日：2019-04-18
申请号：US15553656
申请日：2016-02-24
申请人： In-Young LEE
发明人： In-Young LEE , Kang-Hyung KIM , Hyun-Seok JEON
IPC分类号： C22C23/04 , C22C1/03
摘要： Disclosed is a magnesium alloy that has high thermal conductivity and flame retardancy and facilitates plastic working, wherein magnesium is added with 0.5 to 5 wt % of zinc and 0.6 to 3.5 wt % of tin (Sn) as a high-melting-point oxide-film-forming element, with, as necessary, 1.5 wt % or less of at least one selected from among calcium (Ca), silicon (Si), manganese (Mn) and mischmetal, the total amount of alloy elements being 2.5 to 6.3 wt %. A method of manufacturing the same is also provided, including melting high-melting-point alloy elements in the form of a master alloy in a magnesium—zinc alloy melt, followed by casting, removing a chill from the cast material, diffusion annealing, and then molding through a tempering process such as rolling, extrusion or forging. This magnesium alloy is improved in ductility by the action of alloy elements for inhibiting the formation of plate-like precipitates in a magnesium matrix structure, can be extruded even at a pressure of 1,000 kgf/cm2 or less due to the increased plasticity thereof, and can exhibit thermal conductivity of 100 W/m·K or more and flame retardancy satisfying the requirements for aircraft materials and is thus suitable for use in fields requiring fire safety, thereby realizing wide application thereof as a heat sink or a structural material for portable appliances, vehicles and aircraft components and contributing to weight reduction.

8. 发明申请

US20180030578A1 PLASTIC DEFORMATION MAGNESIUM ALLOY HAVING EXCELLENT THERMAL CONDUCTIVITY AND FLAME RETARDANCY, AND PREPARATION METHOD 审中-公开
公开(公告)号：US20180030578A1
公开(公告)日：2018-02-01
申请号：US15553688
申请日：2016-02-24
申请人： In-Young LEE
发明人： In-Young LEE , Kang-Hyung KIM , Hyun-Seok JEON
IPC分类号： C22C23/04 , C22C1/02
摘要： Disclosed is a magnesium alloy that has high thermal conductivity and flame retardancy and facilitates plastic working, wherein magnesium is added with 0.5 to 5 wt % of zinc (Zn) and 0.3 to 2.0 wt % of at least one of yttrium (Y) and mischmetal, with, as necessary, 1.0 wt % or less of at least one selected from among calcium (Ca), silicon (Si), manganese (Mn) and tin (Sn), the total amount of alloy elements being 2.5 to 6 wt %. A method of manufacturing the same is also provided, including preparing a magnesium-zinc alloy melt in a melting furnace, adding high-melting-point elements in the form of a master alloy and melting them, and performing mechanical stirring during cooling of a cast material in a continuous casting mold containing the magnesium alloy melt, thus producing a magnesium alloy cast material having low segregation, after which a chill is removed from the cast material or diffusion annealing is performed, followed by molding through a tempering process such as rolling, extrusion or forging. This magnesium alloy is improved in ductility by the action of alloy elements for inhibiting the formation of lamella precipitates due to a low-melting-point eutectic phase in a magnesium matrix structure, can be extruded even at a pressure of 1,000 kgf/cm2 or less due to the increased plasticity thereof, and can exhibit thermal conductivity of 100 W/m·K or more and flame retardancy satisfying the requirements for aircraft materials and is thus suitable for use in fields requiring fire safety, thereby realizing wide application thereof as a heat sink or a structural material for portable appliances, vehicles and aircraft components and contributing to weight reduction.

9. 发明申请

US20080036081A1 INTERCONNECTION STRUCTURE OF INTEGRATED CIRCUIT CHIP 有权
标题翻译：集成电路芯片的互连结构
公开(公告)号：US20080036081A1
公开(公告)日：2008-02-14
申请号：US11875713
申请日：2007-10-19
申请人： Se-Young JEONG , Sung-Min SIM , Soon-Bum KIM , In-Young LEE , Young-Hee SONG
发明人： Se-Young JEONG , Sung-Min SIM , Soon-Bum KIM , In-Young LEE , Young-Hee SONG
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/3192 , H01L24/03 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05008 , H01L2224/05018 , H01L2224/05556 , H01L2224/05558 , H01L2224/05571 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.
摘要翻译：互连结构包括具有内部电路的集成电路（IC）芯片和用于将内部电路电连接到外部电路的端子，设置在IC芯片的顶表面上的钝化层，该钝化层被配置为保护内部电路以及使所述终端暴露于所述I / O焊盘包括与所述端子接触的第一部分和在所述钝化层上延伸的第二部分的输入/输出（I / O）焊盘，以及设置在所述钝化层上的无电镀层 I / O板。

10. 发明申请

US20130105988A1 SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP WITH THROUGH OPENING 有权
标题翻译：半导体封装，包括通过开放的半导体芯片
公开(公告)号：US20130105988A1
公开(公告)日：2013-05-02
申请号：US13533473
申请日：2012-06-26
申请人： Chang-Cheol LEE , Hyun-Jun KIM , In-Young LEE , Ki-Kwon JEONG
发明人： Chang-Cheol LEE , Hyun-Jun KIM , In-Young LEE , Ki-Kwon JEONG
IPC分类号： H01L23/48
CPC分类号： H01L23/13 , H01L21/565 , H01L23/49816 , H01L25/0657 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/1815
摘要： A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.
摘要翻译：半导体封装包括具有通过其形成的第一开口的衬底，以倒装芯片方式堆叠在衬底上并具有穿过其中的第二开口的第一半导体芯片，以倒装芯片方式堆叠在第一半导体芯片上的第二半导体芯片，以及具有通过其形成的第三开口，以及覆盖所述第一半导体芯片和所述第二半导体芯片并填充所述基板和所述第一半导体芯片之间的空间的模塑材料，所述第一半导体芯片和所述第二半导体芯片之间的空间，以及填充第一开口，第二开口和第三开口中的每一个。

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